Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	126901063	1			T1	701		T2	85745		T4	296
triple_byte_access	2459870	1			T1	700		T2	1675		T4	8
halfword_access	3790189	1			T1	1084		T2	2485		T4	12
byte_access	5331396	1			T1	1361		T2	3532		T4	17
zero_access	1649884	1			T1	349		T2	884		T4	5

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69707849

1

T1

2048

T2

54279

T4

178

auto[1]

70424553

1

T1

2147

T2

40042

T4

160

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	62971111	1			T1	364		T2	49379		T4	156
auto[0]	triple_byte_access	1161829	1			T1	360		T2	992		T4	5
auto[0]	halfword_access	1841202	1			T1	528		T2	1409		T4	8
auto[0]	byte_access	2733658	1			T1	636		T2	1997		T4	8
auto[0]	zero_access	1000049	1			T1	160		T2	502		T4	1
auto[1]	word_access	63929952	1			T1	337		T2	36366		T4	140
auto[1]	triple_byte_access	1298041	1			T1	340		T2	683		T4	3
auto[1]	halfword_access	1948987	1			T1	556		T2	1076		T4	4
auto[1]	byte_access	2597738	1			T1	725		T2	1535		T4	9
auto[1]	zero_access	649835	1			T1	189		T2	382		T4	4