Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	341604956	1			T1	392586		T2	291526		T3	2250
instr_valid_dis	287891726	1			T1	392586		T2	291526		T3	2250
instr_en	35434426	1			T14	126010		T17	135154		T131	175180

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17561640	1			T11	92774		T14	86098		T17	65712
sram_ifetch_valid_disable	289569192	1			T1	392586		T2	291526		T3	2250
sram_ifetch_enable	34474124	1			T11	112120		T14	171310		T17	129276

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	341604956	1			T1	392586		T2	291526		T3	2250
hw_debug_en_valid_off	292007402	1			T1	392586		T2	291526		T3	2250
hw_debug_en_on	35181656	1			T11	92596		T14	89360		T17	34518

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	289569192	1			T1	392586		T2	291526		T3	2250
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	274925158	1			T1	392586		T2	291526		T3	2250
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8285286	1			T14	28236		T17	60394		T131	76586
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4668626	1			T11	56706		T14	30576		T49	40036
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1826358	1			T11	56706		T23	53404		T128	44258
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1804996	1			T14	30576		T131	20000		T133	73984
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9565812	1			T11	36068		T14	36706		T23	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1794858	1			T11	36068		T14	36706		T23	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	7002184	1			T131	14364		T134	62720		T135	33854
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11657322	1			T14	52654		T17	25552		T49	21202
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3717544	1			T14	52654		T23	57710		T50	103458
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3690050	1			T17	25552		T131	22900		T132	27306

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	17493102	1			T14	67198		T17	9048		T131	64230
lc_exec_en	13958522	1			T11	56528		T17	8966		T49	50746
valid_exec_dis	280596366	1			T1	392586		T2	291526		T3	2250
invalid_exec_dis	52035764	1			T11	204894		T14	257408		T17	194988