Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141824065	1			T1	35798		T2	26355		T3	1125
triple_byte_access	2869136	1			T1	32168		T2	23825		T4	52391
halfword_access	4394688	1			T1	47994		T2	35564		T4	79238
byte_access	6122465	1			T1	64300		T2	48104		T4	105045
zero_access	1832034	1			T1	16033		T2	11915		T4	26119

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78439927

1

T1

98240

T2

72965

T3

536

auto[1]

78602461

1

T1

98053

T2

72798

T3

589

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70695237	1			T1	17800		T2	13291		T3	536
auto[0]	triple_byte_access	1374460	1			T1	16120		T2	11839		T4	26260
auto[0]	halfword_access	2154075	1			T1	24129		T2	17933		T4	39655
auto[0]	byte_access	3131943	1			T1	32190		T2	24014		T4	52379
auto[0]	zero_access	1084212	1			T1	8001		T2	5888		T4	13147
auto[1]	word_access	71128828	1			T1	17998		T2	13064		T3	589
auto[1]	triple_byte_access	1494676	1			T1	16048		T2	11986		T4	26131
auto[1]	halfword_access	2240613	1			T1	23865		T2	17631		T4	39583
auto[1]	byte_access	2990522	1			T1	32110		T2	24090		T4	52666
auto[1]	zero_access	747822	1			T1	8032		T2	6027		T4	12972