Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	344270124	1			T1	337112		T2	5568		T3	125700
instr_valid_dis	309906567	1			T1	337112		T2	5568		T3	125700
instr_en	23380209	1			T14	42106		T5	162052		T30	20372

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14889278	1			T14	1444		T5	85974		T30	14034
sram_ifetch_valid_disable	306102118	1			T1	337112		T2	5568		T3	125700
sram_ifetch_enable	23278728	1			T14	42106		T5	154680		T30	54756

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	344270124	1			T1	337112		T2	5568		T3	125700
hw_debug_en_valid_off	305975398	1			T1	337112		T2	5568		T3	125700
hw_debug_en_on	22643404	1			T14	24808		T5	266758		T30	41184

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	306102118	1			T1	337112		T2	5568		T3	125700
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	294162779	1			T1	337112		T2	5568		T3	125700
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8211255	1			T5	94094		T30	15502		T27	48222
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5542148	1			T14	1444		T5	14226		T54	35974
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3618540	1			T14	1444		T5	826		T54	35974
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1349320	1			T5	13400		T27	6462		T28	90804
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7311302	1			T5	71748		T37	37326		T119	2662
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3851398	1			T5	71748		T47	12456		T128	37326
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2828980	1			T37	37326		T119	2662		T47	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7494092	1			T5	86688		T30	40430		T37	75668
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3004660	1			T5	36820		T30	32222		T47	46780
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3231028	1			T5	49868		T30	8208		T37	32828

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10265144	1			T14	42106		T5	54558		T30	4870
lc_exec_en	7838010	1			T14	24808		T5	108322		T30	754
valid_exec_dis	298935252	1			T1	337112		T2	5568		T3	125700
invalid_exec_dis	38168006	1			T14	43550		T5	240654		T30	68790