Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	143604624	1			T1	153284		T3	57271		T7	42018
triple_byte_access	2800641	1			T1	3087		T3	1159		T7	37773
halfword_access	4297761	1			T1	4537		T3	1589		T7	56348
byte_access	6000711	1			T1	6156		T3	2260		T7	75400
zero_access	1811817	1			T1	1492		T3	571		T7	18868

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78956573

1

T1

84000

T3

31491

T7

115134

auto[1]

79558981

1

T1

84556

T3

31359

T7

115273

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71368656	1			T1	76371		T3	28736		T7	21227
auto[0]	triple_byte_access	1336374	1			T1	1567		T3	577		T7	18868
auto[0]	halfword_access	2101382	1			T1	2266		T3	789		T7	28125
auto[0]	byte_access	3070990	1			T1	3055		T3	1101		T7	37443
auto[0]	zero_access	1079171	1			T1	741		T3	288		T7	9471
auto[1]	word_access	72235968	1			T1	76913		T3	28535		T7	20791
auto[1]	triple_byte_access	1464267	1			T1	1520		T3	582		T7	18905
auto[1]	halfword_access	2196379	1			T1	2271		T3	800		T7	28223
auto[1]	byte_access	2929721	1			T1	3101		T3	1159		T7	37957
auto[1]	zero_access	732646	1			T1	751		T3	283		T7	9397