Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1036
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T791 /workspace/coverage/default/13.sram_ctrl_mem_walk.231788636 May 16 02:43:47 PM PDT 24 May 16 02:45:56 PM PDT 24 2060081155 ps
T792 /workspace/coverage/default/38.sram_ctrl_alert_test.34492619 May 16 02:49:22 PM PDT 24 May 16 02:49:25 PM PDT 24 47603846 ps
T793 /workspace/coverage/default/9.sram_ctrl_bijection.689878442 May 16 02:43:20 PM PDT 24 May 16 03:05:03 PM PDT 24 299090061702 ps
T794 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.579377485 May 16 02:43:44 PM PDT 24 May 16 02:44:59 PM PDT 24 2459783045 ps
T795 /workspace/coverage/default/3.sram_ctrl_alert_test.2198811394 May 16 02:43:05 PM PDT 24 May 16 02:43:12 PM PDT 24 25958822 ps
T796 /workspace/coverage/default/7.sram_ctrl_mem_walk.1211013652 May 16 02:43:27 PM PDT 24 May 16 02:45:34 PM PDT 24 4034562274 ps
T797 /workspace/coverage/default/47.sram_ctrl_executable.454912842 May 16 02:51:16 PM PDT 24 May 16 03:04:08 PM PDT 24 13240765004 ps
T798 /workspace/coverage/default/36.sram_ctrl_executable.756678081 May 16 02:48:38 PM PDT 24 May 16 03:15:51 PM PDT 24 32811593325 ps
T799 /workspace/coverage/default/41.sram_ctrl_alert_test.2893089003 May 16 02:50:07 PM PDT 24 May 16 02:50:09 PM PDT 24 41248805 ps
T800 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2451904784 May 16 02:51:17 PM PDT 24 May 16 02:54:39 PM PDT 24 26505420782 ps
T801 /workspace/coverage/default/3.sram_ctrl_mem_walk.1768230969 May 16 02:43:05 PM PDT 24 May 16 02:45:21 PM PDT 24 6808738670 ps
T802 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.429350713 May 16 02:48:36 PM PDT 24 May 16 02:50:19 PM PDT 24 785477734 ps
T803 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2998668597 May 16 02:47:48 PM PDT 24 May 16 03:05:44 PM PDT 24 10536914561 ps
T804 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.473678710 May 16 02:43:12 PM PDT 24 May 16 02:44:19 PM PDT 24 2566526325 ps
T805 /workspace/coverage/default/9.sram_ctrl_stress_all.3003117613 May 16 02:43:21 PM PDT 24 May 16 03:54:59 PM PDT 24 172467102065 ps
T806 /workspace/coverage/default/43.sram_ctrl_max_throughput.2729711935 May 16 02:50:25 PM PDT 24 May 16 02:51:05 PM PDT 24 2988196185 ps
T807 /workspace/coverage/default/2.sram_ctrl_regwen.2112030900 May 16 02:43:02 PM PDT 24 May 16 02:50:08 PM PDT 24 6414718906 ps
T808 /workspace/coverage/default/14.sram_ctrl_mem_walk.1726249564 May 16 02:43:57 PM PDT 24 May 16 02:48:13 PM PDT 24 4068388012 ps
T809 /workspace/coverage/default/48.sram_ctrl_partial_access.1476433855 May 16 02:51:39 PM PDT 24 May 16 02:51:58 PM PDT 24 1145209264 ps
T810 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2138476005 May 16 02:51:29 PM PDT 24 May 16 02:52:37 PM PDT 24 957037647 ps
T811 /workspace/coverage/default/19.sram_ctrl_lc_escalation.2771265829 May 16 02:44:47 PM PDT 24 May 16 02:44:58 PM PDT 24 1395172714 ps
T812 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3880939570 May 16 02:46:53 PM PDT 24 May 16 02:47:10 PM PDT 24 715004156 ps
T813 /workspace/coverage/default/29.sram_ctrl_executable.3281126454 May 16 02:46:51 PM PDT 24 May 16 02:52:03 PM PDT 24 6124686247 ps
T814 /workspace/coverage/default/34.sram_ctrl_mem_walk.3967986842 May 16 02:48:20 PM PDT 24 May 16 02:50:23 PM PDT 24 2045831446 ps
T815 /workspace/coverage/default/43.sram_ctrl_mem_walk.1484099680 May 16 02:50:38 PM PDT 24 May 16 02:54:42 PM PDT 24 8210123233 ps
T816 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.40727609 May 16 02:51:51 PM PDT 24 May 16 02:56:34 PM PDT 24 12200576809 ps
T817 /workspace/coverage/default/11.sram_ctrl_regwen.2518636688 May 16 02:43:38 PM PDT 24 May 16 02:58:56 PM PDT 24 11355485178 ps
T818 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2610423812 May 16 02:50:16 PM PDT 24 May 16 03:05:19 PM PDT 24 72705761185 ps
T819 /workspace/coverage/default/31.sram_ctrl_executable.3240383030 May 16 02:47:24 PM PDT 24 May 16 03:10:30 PM PDT 24 21487339607 ps
T820 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3048466304 May 16 02:50:59 PM PDT 24 May 16 02:56:34 PM PDT 24 15133068357 ps
T821 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1738165897 May 16 02:49:35 PM PDT 24 May 16 02:50:24 PM PDT 24 1610256933 ps
T822 /workspace/coverage/default/1.sram_ctrl_mem_walk.1558032722 May 16 02:43:03 PM PDT 24 May 16 02:45:48 PM PDT 24 41278401583 ps
T823 /workspace/coverage/default/14.sram_ctrl_lc_escalation.4254482691 May 16 02:43:57 PM PDT 24 May 16 02:45:02 PM PDT 24 33965263098 ps
T824 /workspace/coverage/default/31.sram_ctrl_bijection.424878786 May 16 02:47:14 PM PDT 24 May 16 03:23:44 PM PDT 24 127026709518 ps
T825 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3015427791 May 16 02:51:16 PM PDT 24 May 16 02:54:34 PM PDT 24 8533222556 ps
T826 /workspace/coverage/default/19.sram_ctrl_executable.848579191 May 16 02:44:45 PM PDT 24 May 16 02:46:04 PM PDT 24 4609511365 ps
T827 /workspace/coverage/default/32.sram_ctrl_max_throughput.43586815 May 16 02:47:26 PM PDT 24 May 16 02:47:37 PM PDT 24 2948854746 ps
T828 /workspace/coverage/default/41.sram_ctrl_max_throughput.1359829141 May 16 02:50:09 PM PDT 24 May 16 02:52:25 PM PDT 24 801293372 ps
T829 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.700555523 May 16 02:44:35 PM PDT 24 May 16 02:59:41 PM PDT 24 22136130897 ps
T830 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.4234642427 May 16 02:49:34 PM PDT 24 May 16 02:54:46 PM PDT 24 4895735542 ps
T831 /workspace/coverage/default/31.sram_ctrl_regwen.1633221452 May 16 02:47:23 PM PDT 24 May 16 03:17:59 PM PDT 24 16424315724 ps
T832 /workspace/coverage/default/2.sram_ctrl_max_throughput.1400586735 May 16 02:43:12 PM PDT 24 May 16 02:44:00 PM PDT 24 1116915928 ps
T833 /workspace/coverage/default/35.sram_ctrl_mem_walk.1086652791 May 16 02:48:29 PM PDT 24 May 16 02:52:32 PM PDT 24 10110505877 ps
T834 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1554488402 May 16 02:47:25 PM PDT 24 May 16 02:50:46 PM PDT 24 4211204427 ps
T835 /workspace/coverage/default/12.sram_ctrl_multiple_keys.181042474 May 16 02:43:41 PM PDT 24 May 16 02:47:17 PM PDT 24 8903542350 ps
T836 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3685556553 May 16 02:49:45 PM PDT 24 May 16 02:54:49 PM PDT 24 16084230026 ps
T837 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3539230753 May 16 02:44:54 PM PDT 24 May 16 02:48:38 PM PDT 24 22198739852 ps
T838 /workspace/coverage/default/44.sram_ctrl_executable.3932719975 May 16 02:50:46 PM PDT 24 May 16 02:51:29 PM PDT 24 6559206991 ps
T839 /workspace/coverage/default/15.sram_ctrl_bijection.4137120449 May 16 02:44:03 PM PDT 24 May 16 03:09:31 PM PDT 24 163916187466 ps
T840 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.197914979 May 16 02:43:15 PM PDT 24 May 16 02:45:42 PM PDT 24 6651606290 ps
T841 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.539797070 May 16 02:44:36 PM PDT 24 May 16 02:49:07 PM PDT 24 14891359365 ps
T842 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2903149968 May 16 02:43:21 PM PDT 24 May 16 02:45:43 PM PDT 24 1580413059 ps
T843 /workspace/coverage/default/3.sram_ctrl_stress_all.1624376453 May 16 02:43:05 PM PDT 24 May 16 02:55:51 PM PDT 24 63033423668 ps
T844 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1176089901 May 16 02:43:10 PM PDT 24 May 16 02:44:34 PM PDT 24 2446672428 ps
T845 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.46861612 May 16 02:46:37 PM PDT 24 May 16 02:48:09 PM PDT 24 7668338979 ps
T846 /workspace/coverage/default/0.sram_ctrl_executable.1220614721 May 16 02:42:55 PM PDT 24 May 16 02:59:13 PM PDT 24 14334963626 ps
T847 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2317119730 May 16 02:51:38 PM PDT 24 May 16 02:58:01 PM PDT 24 5257643475 ps
T848 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1862499732 May 16 02:44:09 PM PDT 24 May 16 02:48:47 PM PDT 24 24564514789 ps
T849 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.991171939 May 16 02:43:21 PM PDT 24 May 16 02:48:50 PM PDT 24 22382888692 ps
T850 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1145080075 May 16 02:44:44 PM PDT 24 May 16 02:46:05 PM PDT 24 4912727331 ps
T851 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1539993082 May 16 02:43:25 PM PDT 24 May 16 02:44:33 PM PDT 24 1049955360 ps
T852 /workspace/coverage/default/10.sram_ctrl_alert_test.705052131 May 16 02:43:29 PM PDT 24 May 16 02:43:33 PM PDT 24 14575595 ps
T853 /workspace/coverage/default/35.sram_ctrl_bijection.511791613 May 16 02:48:14 PM PDT 24 May 16 03:02:01 PM PDT 24 194087117798 ps
T854 /workspace/coverage/default/33.sram_ctrl_lc_escalation.753443805 May 16 02:47:43 PM PDT 24 May 16 02:49:01 PM PDT 24 46547846867 ps
T855 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2745054809 May 16 02:48:53 PM PDT 24 May 16 02:52:44 PM PDT 24 24240241489 ps
T856 /workspace/coverage/default/49.sram_ctrl_smoke.3541389221 May 16 02:51:49 PM PDT 24 May 16 02:52:12 PM PDT 24 2689664165 ps
T857 /workspace/coverage/default/38.sram_ctrl_partial_access.1634810380 May 16 02:49:00 PM PDT 24 May 16 02:51:35 PM PDT 24 3689576236 ps
T858 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2719948014 May 16 02:46:25 PM PDT 24 May 16 02:48:42 PM PDT 24 7384850564 ps
T859 /workspace/coverage/default/49.sram_ctrl_mem_walk.4294724237 May 16 02:51:59 PM PDT 24 May 16 02:56:43 PM PDT 24 14352259173 ps
T860 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1404880427 May 16 02:49:11 PM PDT 24 May 16 03:01:45 PM PDT 24 11038950176 ps
T861 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3971858605 May 16 02:49:35 PM PDT 24 May 16 02:50:27 PM PDT 24 8729018647 ps
T862 /workspace/coverage/default/24.sram_ctrl_regwen.3409501808 May 16 02:45:46 PM PDT 24 May 16 03:09:43 PM PDT 24 13712107263 ps
T863 /workspace/coverage/default/20.sram_ctrl_multiple_keys.3285519537 May 16 02:44:52 PM PDT 24 May 16 03:07:37 PM PDT 24 35408558685 ps
T864 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.930343167 May 16 02:50:09 PM PDT 24 May 16 02:51:09 PM PDT 24 2332868418 ps
T865 /workspace/coverage/default/0.sram_ctrl_bijection.3441317296 May 16 02:42:57 PM PDT 24 May 16 02:52:39 PM PDT 24 34740017930 ps
T866 /workspace/coverage/default/25.sram_ctrl_mem_walk.3958436584 May 16 02:46:02 PM PDT 24 May 16 02:48:06 PM PDT 24 12341148042 ps
T867 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3292433754 May 16 02:46:00 PM PDT 24 May 16 02:53:50 PM PDT 24 72411634765 ps
T868 /workspace/coverage/default/11.sram_ctrl_alert_test.3361414086 May 16 02:43:40 PM PDT 24 May 16 02:43:43 PM PDT 24 14592644 ps
T869 /workspace/coverage/default/24.sram_ctrl_stress_all.3455686730 May 16 02:45:49 PM PDT 24 May 16 04:13:58 PM PDT 24 154248219544 ps
T870 /workspace/coverage/default/7.sram_ctrl_executable.3766168988 May 16 02:43:24 PM PDT 24 May 16 02:55:07 PM PDT 24 30272490991 ps
T871 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1228076564 May 16 02:43:21 PM PDT 24 May 16 02:45:48 PM PDT 24 4991535981 ps
T872 /workspace/coverage/default/27.sram_ctrl_bijection.2110323556 May 16 02:46:19 PM PDT 24 May 16 03:04:37 PM PDT 24 249183303119 ps
T873 /workspace/coverage/default/8.sram_ctrl_partial_access.3432630011 May 16 02:43:24 PM PDT 24 May 16 02:43:42 PM PDT 24 3648272663 ps
T874 /workspace/coverage/default/19.sram_ctrl_alert_test.1216428482 May 16 02:44:53 PM PDT 24 May 16 02:44:56 PM PDT 24 35820059 ps
T875 /workspace/coverage/default/38.sram_ctrl_multiple_keys.2553813752 May 16 02:49:01 PM PDT 24 May 16 03:08:36 PM PDT 24 78302866820 ps
T876 /workspace/coverage/default/38.sram_ctrl_regwen.958587643 May 16 02:49:10 PM PDT 24 May 16 03:10:48 PM PDT 24 37143873028 ps
T877 /workspace/coverage/default/1.sram_ctrl_regwen.402656458 May 16 02:43:11 PM PDT 24 May 16 03:06:55 PM PDT 24 5658232373 ps
T878 /workspace/coverage/default/16.sram_ctrl_partial_access.208646969 May 16 02:44:10 PM PDT 24 May 16 02:44:18 PM PDT 24 2159301530 ps
T879 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4192994086 May 16 02:44:44 PM PDT 24 May 16 03:02:15 PM PDT 24 27555227312 ps
T880 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1851585543 May 16 02:46:35 PM PDT 24 May 16 02:52:39 PM PDT 24 50325143504 ps
T881 /workspace/coverage/default/22.sram_ctrl_regwen.3613543920 May 16 02:45:17 PM PDT 24 May 16 02:56:13 PM PDT 24 9507888708 ps
T882 /workspace/coverage/default/21.sram_ctrl_partial_access.3467365480 May 16 02:45:02 PM PDT 24 May 16 02:45:15 PM PDT 24 3818772680 ps
T883 /workspace/coverage/default/13.sram_ctrl_executable.442466003 May 16 02:43:48 PM PDT 24 May 16 02:59:18 PM PDT 24 7354245685 ps
T884 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3462547634 May 16 02:47:21 PM PDT 24 May 16 02:52:44 PM PDT 24 9026759399 ps
T885 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3637778023 May 16 02:43:56 PM PDT 24 May 16 02:44:37 PM PDT 24 2914024083 ps
T886 /workspace/coverage/default/40.sram_ctrl_stress_all.3958948238 May 16 02:49:47 PM PDT 24 May 16 03:45:43 PM PDT 24 96977280353 ps
T887 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3338703634 May 16 02:43:45 PM PDT 24 May 16 02:48:58 PM PDT 24 2932441620 ps
T888 /workspace/coverage/default/21.sram_ctrl_stress_all.613939018 May 16 02:45:12 PM PDT 24 May 16 03:26:58 PM PDT 24 30475389973 ps
T889 /workspace/coverage/default/35.sram_ctrl_executable.2183526348 May 16 02:48:20 PM PDT 24 May 16 02:57:30 PM PDT 24 52889423345 ps
T890 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1094906151 May 16 02:50:36 PM PDT 24 May 16 02:50:41 PM PDT 24 3363248250 ps
T891 /workspace/coverage/default/21.sram_ctrl_bijection.423508715 May 16 02:45:03 PM PDT 24 May 16 03:12:11 PM PDT 24 206094850615 ps
T892 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2901197293 May 16 02:44:28 PM PDT 24 May 16 02:44:56 PM PDT 24 1415135574 ps
T893 /workspace/coverage/default/30.sram_ctrl_alert_test.4210622271 May 16 02:47:00 PM PDT 24 May 16 02:47:01 PM PDT 24 14725726 ps
T894 /workspace/coverage/default/13.sram_ctrl_lc_escalation.478582370 May 16 02:43:48 PM PDT 24 May 16 02:45:14 PM PDT 24 12520678291 ps
T895 /workspace/coverage/default/48.sram_ctrl_max_throughput.179554972 May 16 02:51:38 PM PDT 24 May 16 02:51:49 PM PDT 24 700820530 ps
T896 /workspace/coverage/default/3.sram_ctrl_bijection.3740212322 May 16 02:43:04 PM PDT 24 May 16 03:12:24 PM PDT 24 78383533372 ps
T897 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3768716717 May 16 02:46:51 PM PDT 24 May 16 02:46:56 PM PDT 24 361807656 ps
T898 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.542390683 May 16 02:47:41 PM PDT 24 May 16 02:51:05 PM PDT 24 11892457185 ps
T899 /workspace/coverage/default/36.sram_ctrl_regwen.3436878722 May 16 02:48:36 PM PDT 24 May 16 02:55:40 PM PDT 24 20559964985 ps
T900 /workspace/coverage/default/19.sram_ctrl_stress_all.1416957751 May 16 02:44:43 PM PDT 24 May 16 03:59:35 PM PDT 24 387460542579 ps
T901 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1963885038 May 16 02:48:44 PM PDT 24 May 16 03:22:40 PM PDT 24 16727956009 ps
T902 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4105027845 May 16 02:47:42 PM PDT 24 May 16 02:52:12 PM PDT 24 51168783404 ps
T903 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.723553415 May 16 02:50:36 PM PDT 24 May 16 02:52:50 PM PDT 24 1572522714 ps
T904 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1111504318 May 16 02:43:38 PM PDT 24 May 16 03:00:13 PM PDT 24 33207368675 ps
T905 /workspace/coverage/default/27.sram_ctrl_ram_cfg.3079228066 May 16 02:46:27 PM PDT 24 May 16 02:46:34 PM PDT 24 1480557981 ps
T906 /workspace/coverage/default/5.sram_ctrl_executable.3613529945 May 16 02:43:13 PM PDT 24 May 16 02:59:59 PM PDT 24 28911110479 ps
T907 /workspace/coverage/default/49.sram_ctrl_bijection.2873141342 May 16 02:51:50 PM PDT 24 May 16 03:41:19 PM PDT 24 689623928569 ps
T908 /workspace/coverage/default/28.sram_ctrl_lc_escalation.181589774 May 16 02:46:34 PM PDT 24 May 16 02:48:19 PM PDT 24 17420577614 ps
T909 /workspace/coverage/default/8.sram_ctrl_max_throughput.615493373 May 16 02:43:24 PM PDT 24 May 16 02:44:14 PM PDT 24 2934443549 ps
T910 /workspace/coverage/default/46.sram_ctrl_executable.2290680878 May 16 02:51:10 PM PDT 24 May 16 03:04:43 PM PDT 24 5408362863 ps
T911 /workspace/coverage/default/21.sram_ctrl_executable.1084044100 May 16 02:45:01 PM PDT 24 May 16 03:04:00 PM PDT 24 62521418514 ps
T912 /workspace/coverage/default/20.sram_ctrl_regwen.3631379510 May 16 02:44:52 PM PDT 24 May 16 02:53:59 PM PDT 24 13411802950 ps
T913 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4179351713 May 16 02:43:19 PM PDT 24 May 16 02:57:13 PM PDT 24 26364353114 ps
T914 /workspace/coverage/default/45.sram_ctrl_bijection.2778127025 May 16 02:50:59 PM PDT 24 May 16 03:34:17 PM PDT 24 143244997856 ps
T915 /workspace/coverage/default/29.sram_ctrl_regwen.1580405423 May 16 02:46:56 PM PDT 24 May 16 03:16:05 PM PDT 24 75431676101 ps
T916 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3204355632 May 16 02:49:28 PM PDT 24 May 16 02:53:30 PM PDT 24 37712563786 ps
T917 /workspace/coverage/default/6.sram_ctrl_max_throughput.518008916 May 16 02:43:13 PM PDT 24 May 16 02:43:41 PM PDT 24 1469008649 ps
T918 /workspace/coverage/default/39.sram_ctrl_smoke.912031810 May 16 02:49:19 PM PDT 24 May 16 02:50:06 PM PDT 24 654082528 ps
T919 /workspace/coverage/default/34.sram_ctrl_bijection.2358630671 May 16 02:47:58 PM PDT 24 May 16 03:12:39 PM PDT 24 48433024999 ps
T920 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1300134778 May 16 02:43:11 PM PDT 24 May 16 02:43:26 PM PDT 24 266997774 ps
T921 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3520093992 May 16 02:43:29 PM PDT 24 May 16 02:44:51 PM PDT 24 2373999879 ps
T922 /workspace/coverage/default/4.sram_ctrl_regwen.3954696535 May 16 02:43:15 PM PDT 24 May 16 03:07:56 PM PDT 24 105026388672 ps
T923 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1168768335 May 16 02:45:38 PM PDT 24 May 16 02:46:09 PM PDT 24 1029778347 ps
T924 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.682315073 May 16 02:51:10 PM PDT 24 May 16 02:58:45 PM PDT 24 28146418183 ps
T925 /workspace/coverage/default/29.sram_ctrl_smoke.1014955388 May 16 02:46:47 PM PDT 24 May 16 02:48:19 PM PDT 24 1684356076 ps
T926 /workspace/coverage/default/7.sram_ctrl_partial_access.1582402788 May 16 02:43:23 PM PDT 24 May 16 02:43:39 PM PDT 24 1589092262 ps
T927 /workspace/coverage/default/24.sram_ctrl_executable.1207937243 May 16 02:45:43 PM PDT 24 May 16 02:57:46 PM PDT 24 18695226506 ps
T928 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.437138972 May 16 02:47:23 PM PDT 24 May 16 02:48:02 PM PDT 24 4964744663 ps
T929 /workspace/coverage/default/21.sram_ctrl_smoke.341816949 May 16 02:45:03 PM PDT 24 May 16 02:45:28 PM PDT 24 6338484340 ps
T930 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3813358107 May 16 02:43:14 PM PDT 24 May 16 02:44:41 PM PDT 24 28211790668 ps
T931 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1468767748 May 16 02:49:00 PM PDT 24 May 16 02:52:48 PM PDT 24 17171535340 ps
T932 /workspace/coverage/default/49.sram_ctrl_multiple_keys.4281008144 May 16 02:51:48 PM PDT 24 May 16 03:03:28 PM PDT 24 44260394799 ps
T933 /workspace/coverage/default/7.sram_ctrl_ram_cfg.57248496 May 16 02:43:20 PM PDT 24 May 16 02:43:27 PM PDT 24 1618457010 ps
T934 /workspace/coverage/default/28.sram_ctrl_stress_all.2453396266 May 16 02:46:41 PM PDT 24 May 16 04:01:17 PM PDT 24 50792371664 ps
T935 /workspace/coverage/default/45.sram_ctrl_mem_walk.2512781474 May 16 02:50:59 PM PDT 24 May 16 02:56:23 PM PDT 24 43023925499 ps
T936 /workspace/coverage/default/13.sram_ctrl_smoke.3336898246 May 16 02:43:48 PM PDT 24 May 16 02:43:59 PM PDT 24 1432588885 ps
T937 /workspace/coverage/default/12.sram_ctrl_max_throughput.2952816077 May 16 02:43:37 PM PDT 24 May 16 02:43:45 PM PDT 24 3022135876 ps
T938 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.115011552 May 16 02:50:47 PM PDT 24 May 16 02:52:00 PM PDT 24 1463528061 ps
T939 /workspace/coverage/default/36.sram_ctrl_lc_escalation.96269324 May 16 02:48:36 PM PDT 24 May 16 02:49:40 PM PDT 24 10974318126 ps
T940 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.101222094 May 16 02:45:43 PM PDT 24 May 16 02:48:32 PM PDT 24 5900780408 ps
T941 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3156999018 May 16 02:43:46 PM PDT 24 May 16 02:46:11 PM PDT 24 1624056458 ps
T88 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1982647551 May 16 02:41:46 PM PDT 24 May 16 02:41:48 PM PDT 24 44998531 ps
T94 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2250170 May 16 02:41:49 PM PDT 24 May 16 02:41:53 PM PDT 24 22058307 ps
T96 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1913254047 May 16 02:41:52 PM PDT 24 May 16 02:41:58 PM PDT 24 328728210 ps
T58 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2048719050 May 16 02:42:01 PM PDT 24 May 16 02:42:33 PM PDT 24 4454455622 ps
T942 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3660025511 May 16 02:41:39 PM PDT 24 May 16 02:41:45 PM PDT 24 362207643 ps
T943 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3397147022 May 16 02:41:51 PM PDT 24 May 16 02:41:59 PM PDT 24 118499439 ps
T944 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2818198907 May 16 02:41:49 PM PDT 24 May 16 02:41:56 PM PDT 24 366551787 ps
T59 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1436327206 May 16 02:42:09 PM PDT 24 May 16 02:42:15 PM PDT 24 29816587 ps
T95 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1506034385 May 16 02:41:52 PM PDT 24 May 16 02:41:57 PM PDT 24 17217559 ps
T60 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4119413462 May 16 02:41:59 PM PDT 24 May 16 02:42:31 PM PDT 24 4205574772 ps
T945 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2956313790 May 16 02:41:49 PM PDT 24 May 16 02:41:54 PM PDT 24 136984048 ps
T946 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2216682639 May 16 02:41:47 PM PDT 24 May 16 02:41:51 PM PDT 24 276320594 ps
T97 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2762673192 May 16 02:41:58 PM PDT 24 May 16 02:42:03 PM PDT 24 210708464 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2456205960 May 16 02:41:39 PM PDT 24 May 16 02:42:21 PM PDT 24 33577742037 ps
T947 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4023994640 May 16 02:41:41 PM PDT 24 May 16 02:41:47 PM PDT 24 27513865 ps
T61 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3487584368 May 16 02:41:50 PM PDT 24 May 16 02:42:26 PM PDT 24 16037124657 ps
T62 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1306316871 May 16 02:41:49 PM PDT 24 May 16 02:42:20 PM PDT 24 14748479282 ps
T948 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3930515909 May 16 02:41:50 PM PDT 24 May 16 02:41:58 PM PDT 24 360285012 ps
T949 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1457692507 May 16 02:42:00 PM PDT 24 May 16 02:42:07 PM PDT 24 713356221 ps
T63 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.767811154 May 16 02:41:59 PM PDT 24 May 16 02:42:03 PM PDT 24 42609423 ps
T98 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.436729535 May 16 02:41:57 PM PDT 24 May 16 02:42:01 PM PDT 24 168448037 ps
T112 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2135871764 May 16 02:41:50 PM PDT 24 May 16 02:41:55 PM PDT 24 175317981 ps
T950 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2416138007 May 16 02:41:38 PM PDT 24 May 16 02:41:42 PM PDT 24 53875522 ps
T951 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.557473159 May 16 02:41:47 PM PDT 24 May 16 02:41:54 PM PDT 24 356505135 ps
T90 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2948176203 May 16 02:41:46 PM PDT 24 May 16 02:41:49 PM PDT 24 55364231 ps
T109 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1175446263 May 16 02:41:45 PM PDT 24 May 16 02:41:49 PM PDT 24 777117654 ps
T952 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3396096916 May 16 02:41:49 PM PDT 24 May 16 02:41:55 PM PDT 24 63103491 ps
T953 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3153697308 May 16 02:42:07 PM PDT 24 May 16 02:42:15 PM PDT 24 118887109 ps
T954 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3493361886 May 16 02:41:40 PM PDT 24 May 16 02:41:45 PM PDT 24 341781698 ps
T91 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1632397139 May 16 02:41:58 PM PDT 24 May 16 02:42:03 PM PDT 24 63836395 ps
T64 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3801505741 May 16 02:41:47 PM PDT 24 May 16 02:42:18 PM PDT 24 23128700369 ps
T955 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2864833392 May 16 02:42:00 PM PDT 24 May 16 02:42:04 PM PDT 24 55487402 ps
T111 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1680155149 May 16 02:42:08 PM PDT 24 May 16 02:42:14 PM PDT 24 224268832 ps
T956 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.729724964 May 16 02:41:56 PM PDT 24 May 16 02:42:03 PM PDT 24 1404670412 ps
T957 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3314269768 May 16 02:41:41 PM PDT 24 May 16 02:41:45 PM PDT 24 13750775 ps
T958 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4129501483 May 16 02:41:48 PM PDT 24 May 16 02:41:52 PM PDT 24 16565323 ps
T959 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.836624829 May 16 02:42:09 PM PDT 24 May 16 02:42:14 PM PDT 24 17154720 ps
T65 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3361279040 May 16 02:41:39 PM PDT 24 May 16 02:42:11 PM PDT 24 16745918253 ps
T960 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2599089766 May 16 02:42:08 PM PDT 24 May 16 02:42:14 PM PDT 24 36350614 ps
T116 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1103523430 May 16 02:42:00 PM PDT 24 May 16 02:42:05 PM PDT 24 85935655 ps
T66 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2374566666 May 16 02:41:40 PM PDT 24 May 16 02:41:45 PM PDT 24 149845840 ps
T110 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.823229315 May 16 02:41:58 PM PDT 24 May 16 02:42:04 PM PDT 24 167963944 ps
T961 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3861158116 May 16 02:41:49 PM PDT 24 May 16 02:41:53 PM PDT 24 23289695 ps
T962 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2187424300 May 16 02:41:48 PM PDT 24 May 16 02:41:52 PM PDT 24 54550235 ps
T67 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.376119137 May 16 02:41:49 PM PDT 24 May 16 02:41:54 PM PDT 24 118571616 ps
T963 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3289438878 May 16 02:41:47 PM PDT 24 May 16 02:41:53 PM PDT 24 1606658850 ps
T117 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4287416482 May 16 02:41:50 PM PDT 24 May 16 02:41:56 PM PDT 24 494811052 ps
T964 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1387359982 May 16 02:41:59 PM PDT 24 May 16 02:42:08 PM PDT 24 269446978 ps
T965 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3243369878 May 16 02:41:48 PM PDT 24 May 16 02:41:53 PM PDT 24 86631489 ps
T70 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1866726009 May 16 02:41:49 PM PDT 24 May 16 02:42:41 PM PDT 24 14121660977 ps
T966 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3579611569 May 16 02:41:57 PM PDT 24 May 16 02:42:01 PM PDT 24 42522166 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3392298020 May 16 02:41:32 PM PDT 24 May 16 02:41:40 PM PDT 24 153254789 ps
T968 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1596513857 May 16 02:41:58 PM PDT 24 May 16 02:42:02 PM PDT 24 45057776 ps
T969 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2030117220 May 16 02:42:08 PM PDT 24 May 16 02:42:13 PM PDT 24 171736343 ps
T115 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3032025342 May 16 02:41:48 PM PDT 24 May 16 02:41:52 PM PDT 24 172898163 ps
T970 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3476722041 May 16 02:41:39 PM PDT 24 May 16 02:41:45 PM PDT 24 71439964 ps
T971 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3421216581 May 16 02:41:59 PM PDT 24 May 16 02:42:06 PM PDT 24 749045237 ps
T972 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.492898703 May 16 02:41:41 PM PDT 24 May 16 02:41:45 PM PDT 24 43557127 ps
T113 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.630713368 May 16 02:41:39 PM PDT 24 May 16 02:41:44 PM PDT 24 278750470 ps
T973 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3052925178 May 16 02:41:41 PM PDT 24 May 16 02:41:45 PM PDT 24 15239986 ps
T974 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4095621150 May 16 02:41:52 PM PDT 24 May 16 02:41:59 PM PDT 24 728577580 ps
T71 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2633025192 May 16 02:41:48 PM PDT 24 May 16 02:42:22 PM PDT 24 13696399925 ps
T975 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2209900254 May 16 02:41:38 PM PDT 24 May 16 02:41:43 PM PDT 24 239309611 ps
T976 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3363314602 May 16 02:41:51 PM PDT 24 May 16 02:41:59 PM PDT 24 1382311009 ps
T977 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2323568350 May 16 02:41:41 PM PDT 24 May 16 02:41:45 PM PDT 24 33427065 ps
T72 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3752864800 May 16 02:41:58 PM PDT 24 May 16 02:42:29 PM PDT 24 15370365823 ps
T114 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.239608615 May 16 02:42:08 PM PDT 24 May 16 02:42:14 PM PDT 24 147587364 ps
T73 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4101666743 May 16 02:41:51 PM PDT 24 May 16 02:42:41 PM PDT 24 7239737597 ps
T978 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2317789906 May 16 02:41:45 PM PDT 24 May 16 02:41:48 PM PDT 24 45566040 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3715938340 May 16 02:41:50 PM PDT 24 May 16 02:41:55 PM PDT 24 14182972 ps
T980 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2615375315 May 16 02:41:40 PM PDT 24 May 16 02:41:44 PM PDT 24 32440281 ps
T981 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3672315750 May 16 02:41:58 PM PDT 24 May 16 02:42:04 PM PDT 24 1065709570 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1707689873 May 16 02:41:45 PM PDT 24 May 16 02:41:48 PM PDT 24 25178681 ps
T79 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3445702130 May 16 02:41:59 PM PDT 24 May 16 02:42:03 PM PDT 24 14865568 ps
T983 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.272505787 May 16 02:42:07 PM PDT 24 May 16 02:42:36 PM PDT 24 3769828685 ps
T84 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.89390147 May 16 02:41:52 PM PDT 24 May 16 02:41:57 PM PDT 24 14005244 ps
T984 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1632709222 May 16 02:42:08 PM PDT 24 May 16 02:43:06 PM PDT 24 28181153550 ps
T85 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2397961472 May 16 02:42:00 PM PDT 24 May 16 02:42:04 PM PDT 24 42833371 ps
T80 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2926002323 May 16 02:41:41 PM PDT 24 May 16 02:41:46 PM PDT 24 712295839 ps
T985 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2623921062 May 16 02:41:48 PM PDT 24 May 16 02:41:51 PM PDT 24 23128580 ps
T986 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2590077411 May 16 02:42:09 PM PDT 24 May 16 02:42:14 PM PDT 24 73312508 ps
T987 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3800881768 May 16 02:41:42 PM PDT 24 May 16 02:41:45 PM PDT 24 45396305 ps
T988 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2771151925 May 16 02:41:51 PM PDT 24 May 16 02:41:59 PM PDT 24 378049053 ps
T989 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1167363243 May 16 02:41:41 PM PDT 24 May 16 02:41:49 PM PDT 24 370998298 ps
T990 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.192950500 May 16 02:42:10 PM PDT 24 May 16 02:42:19 PM PDT 24 763974843 ps
T991 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4215184582 May 16 02:41:56 PM PDT 24 May 16 02:42:02 PM PDT 24 354678154 ps
T992 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.11500132 May 16 02:42:09 PM PDT 24 May 16 02:42:15 PM PDT 24 51083549 ps
T993 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3187485934 May 16 02:41:48 PM PDT 24 May 16 02:41:53 PM PDT 24 47433735 ps
T994 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.910901743 May 16 02:41:58 PM PDT 24 May 16 02:42:03 PM PDT 24 44888451 ps
T995 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3947111662 May 16 02:41:49 PM PDT 24 May 16 02:41:53 PM PDT 24 22979681 ps
T996 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1415880843 May 16 02:41:41 PM PDT 24 May 16 02:41:45 PM PDT 24 27339673 ps
T997 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3332605954 May 16 02:41:32 PM PDT 24 May 16 02:41:39 PM PDT 24 533745499 ps
T998 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1883096703 May 16 02:41:38 PM PDT 24 May 16 02:42:10 PM PDT 24 21702758206 ps
T999 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2104716247 May 16 02:41:48 PM PDT 24 May 16 02:41:52 PM PDT 24 96170732 ps
T1000 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1472455810 May 16 02:41:50 PM PDT 24 May 16 02:41:55 PM PDT 24 92081992 ps
T118 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2516247089 May 16 02:41:48 PM PDT 24 May 16 02:41:53 PM PDT 24 137766224 ps
T1001 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1237897410 May 16 02:41:58 PM PDT 24 May 16 02:42:04 PM PDT 24 208057884 ps
T1002 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2846254190 May 16 02:41:38 PM PDT 24 May 16 02:41:43 PM PDT 24 23366366 ps
T1003 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.980677937 May 16 02:41:30 PM PDT 24 May 16 02:41:36 PM PDT 24 153781896 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%