Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	371710616	1			T1	530822		T3	304832		T4	42232
instr_valid_dis	330465373	1			T1	530822		T3	19872		T9	20000
instr_en	25265879	1			T3	171100		T4	42232		T18	188850

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12134386	1			T3	20000		T4	31190		T18	39754
sram_ifetch_valid_disable	328644547	1			T1	530822		T3	86328		T4	11042
sram_ifetch_enable	30931683	1			T3	198504		T18	88458		T6	130034

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	371710616	1			T1	530822		T3	304832		T4	42232
hw_debug_en_valid_off	329785289	1			T1	530822		T3	167478		T4	11042
hw_debug_en_on	26794379	1			T3	103124		T18	81918		T6	140838

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	328644547	1			T1	530822		T3	86328		T4	11042
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	317388635	1			T1	530822		T3	19872		T9	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7369016	1			T3	66456		T4	11042		T18	60638
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3959266	1			T3	20000		T18	26912		T6	30896
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1951608	1			T6	30896		T46	18098		T127	16624
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1426102	1			T3	20000		T18	26912		T42	12778
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5949610	1			T18	12842		T6	23922		T42	9102
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1690674	1			T6	23922		T126	22480		T133	5350
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1944760	1			T18	12842		T42	9102		T123	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8710540	1			T3	50112		T18	46302		T6	112364
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4151494	1			T3	19872		T6	28024		T42	31342
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3290634	1			T3	30240		T18	46302		T6	71304

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13485445	1			T3	84644		T18	88458		T6	71000
lc_exec_en	12134229	1			T3	53012		T18	22774		T6	4552
valid_exec_dis	324393793	1			T1	530822		T3	2060		T4	11042
invalid_exec_dis	43066069	1			T3	218504		T4	31190		T18	128212