Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	156528259	1			T1	48388		T3	67869		T4	7691
triple_byte_access	2915231	1			T1	43312		T3	1381		T4	156
halfword_access	4480001	1			T1	65173		T3	2051		T4	238
byte_access	6258710	1			T1	86766		T3	2669		T4	311
zero_access	1898393	1			T1	21772		T3	709		T4	84

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85800506

1

T1

132624

T3

44131

T4

4241

auto[1]

86280088

1

T1

132787

T3

30548

T4

4239

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	77887775	1			T1	24227		T3	40100		T4	3858
auto[0]	triple_byte_access	1389461	1			T1	21588		T3	797		T4	81
auto[0]	halfword_access	2186144	1			T1	32400		T3	1197		T4	112
auto[0]	byte_access	3203410	1			T1	43449		T3	1620		T4	150
auto[0]	zero_access	1133716	1			T1	10960		T3	417		T4	40
auto[1]	word_access	78640484	1			T1	24161		T3	27769		T4	3833
auto[1]	triple_byte_access	1525770	1			T1	21724		T3	584		T4	75
auto[1]	halfword_access	2293857	1			T1	32773		T3	854		T4	126
auto[1]	byte_access	3055300	1			T1	43317		T3	1049		T4	161
auto[1]	zero_access	764677	1			T1	10812		T3	292		T4	44