Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	355072802	1			T1	11368		T2	313334		T3	393212
instr_valid_dis	307439741	1			T1	11368		T2	252836		T3	393212
instr_en	34045525	1			T2	54622		T20	17240		T25	65940

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17185335	1			T2	2470		T13	109784		T119	20088
sram_ifetch_valid_disable	311369909	1			T1	11368		T2	281204		T3	393212
sram_ifetch_enable	26517558	1			T2	29660		T20	30144		T25	152624

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	355072802	1			T1	11368		T2	313334		T3	393212
hw_debug_en_valid_off	310673241	1			T1	11368		T2	252242		T3	393212
hw_debug_en_on	30637307	1			T2	36850		T20	16962		T25	146752

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	311369909	1			T1	11368		T2	281204		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	294797612	1			T1	11368		T2	223176		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10134755	1			T2	52152		T20	4058		T25	65940
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5095328	1			T2	2470		T13	67272		T16	184366
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1583670	1			T13	2318		T52	12410		T19	10632
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2640322	1			T2	2470		T13	35528		T16	68224
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9826219	1			T13	42512		T16	24528		T52	13766
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1573761	1			T13	22586		T122	52906		T121	13976
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	7555500	1			T13	19926		T16	14442		T52	13766
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11144802	1			T2	36850		T25	84230		T13	18352
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3640158	1			T25	54702		T13	2642		T16	56146
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3643802	1			T2	30974		T13	15710		T16	62416

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12442092	1			T20	13182		T13	181042		T16	361854
lc_exec_en	9666286	1			T20	16962		T25	62522		T13	181024
valid_exec_dis	302031303	1			T1	11368		T2	274014		T3	393212
invalid_exec_dis	43702893	1			T2	32130		T20	30144		T25	152624