Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	146348667	1			T1	5164		T2	99054		T3	196606
triple_byte_access	2912519	1			T1	95		T2	1952		T5	27
halfword_access	4469844	1			T1	165		T2	2914		T5	39
byte_access	6254089	1			T1	209		T2	3960		T5	38
zero_access	1901826	1			T1	51		T2	963		T5	13

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80747227

1

T1

2833

T2

56401

T3

65536

auto[1]

81139718

1

T1

2851

T2

52442

T3

131070

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72831335	1			T1	2574		T2	51288		T3	65536
auto[0]	triple_byte_access	1387046	1			T1	46		T2	1029		T5	16
auto[0]	halfword_access	2183389	1			T1	81		T2	1493		T5	18
auto[0]	byte_access	3205763	1			T1	111		T2	2085		T5	20
auto[0]	zero_access	1139694	1			T1	21		T2	506		T5	4
auto[1]	word_access	73517332	1			T1	2590		T2	47766		T3	131070
auto[1]	triple_byte_access	1525473	1			T1	49		T2	923		T5	11
auto[1]	halfword_access	2286455	1			T1	84		T2	1421		T5	21
auto[1]	byte_access	3048326	1			T1	98		T2	1875		T5	18
auto[1]	zero_access	762132	1			T1	30		T2	457		T5	9