| T794 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2555325323 |
|
|
Jun 07 06:26:34 PM PDT 24 |
Jun 07 07:41:34 PM PDT 24 |
963673154702 ps |
| T795 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3137592561 |
|
|
Jun 07 06:21:05 PM PDT 24 |
Jun 07 07:48:43 PM PDT 24 |
177285208079 ps |
| T796 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2391269768 |
|
|
Jun 07 06:27:54 PM PDT 24 |
Jun 07 06:29:00 PM PDT 24 |
1019217477 ps |
| T797 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2417777134 |
|
|
Jun 07 06:21:52 PM PDT 24 |
Jun 07 08:30:19 PM PDT 24 |
206672935911 ps |
| T798 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.238826405 |
|
|
Jun 07 06:25:32 PM PDT 24 |
Jun 07 06:26:42 PM PDT 24 |
6142452881 ps |
| T799 |
/workspace/coverage/default/40.sram_ctrl_stress_all.1509594765 |
|
|
Jun 07 06:26:45 PM PDT 24 |
Jun 07 08:03:50 PM PDT 24 |
258561760820 ps |
| T800 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1243422987 |
|
|
Jun 07 06:22:38 PM PDT 24 |
Jun 07 06:23:04 PM PDT 24 |
2070926373 ps |
| T801 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3416081415 |
|
|
Jun 07 06:27:50 PM PDT 24 |
Jun 07 06:30:43 PM PDT 24 |
5565879912 ps |
| T802 |
/workspace/coverage/default/26.sram_ctrl_regwen.3800621006 |
|
|
Jun 07 06:25:22 PM PDT 24 |
Jun 07 06:34:44 PM PDT 24 |
19233071392 ps |
| T803 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3650863327 |
|
|
Jun 07 06:20:56 PM PDT 24 |
Jun 07 06:26:16 PM PDT 24 |
4882716598 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.586235172 |
|
|
Jun 07 06:21:54 PM PDT 24 |
Jun 07 06:30:21 PM PDT 24 |
83484923365 ps |
| T805 |
/workspace/coverage/default/2.sram_ctrl_bijection.3526031821 |
|
|
Jun 07 06:21:01 PM PDT 24 |
Jun 07 06:48:42 PM PDT 24 |
71230053451 ps |
| T806 |
/workspace/coverage/default/25.sram_ctrl_regwen.4052881815 |
|
|
Jun 07 06:25:12 PM PDT 24 |
Jun 07 06:35:17 PM PDT 24 |
2051620681 ps |
| T807 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3740626415 |
|
|
Jun 07 06:22:32 PM PDT 24 |
Jun 07 06:25:21 PM PDT 24 |
22254362219 ps |
| T808 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2435455327 |
|
|
Jun 07 06:26:08 PM PDT 24 |
Jun 07 06:28:43 PM PDT 24 |
995044220 ps |
| T809 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2618697795 |
|
|
Jun 07 06:21:19 PM PDT 24 |
Jun 07 06:29:21 PM PDT 24 |
190952245996 ps |
| T810 |
/workspace/coverage/default/0.sram_ctrl_regwen.1227715402 |
|
|
Jun 07 06:20:58 PM PDT 24 |
Jun 07 06:44:47 PM PDT 24 |
2392997682 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3296699160 |
|
|
Jun 07 06:21:57 PM PDT 24 |
Jun 07 06:22:10 PM PDT 24 |
2744003861 ps |
| T812 |
/workspace/coverage/default/43.sram_ctrl_partial_access.824102099 |
|
|
Jun 07 06:27:08 PM PDT 24 |
Jun 07 06:27:48 PM PDT 24 |
8171875551 ps |
| T813 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3103612228 |
|
|
Jun 07 06:22:56 PM PDT 24 |
Jun 07 06:25:44 PM PDT 24 |
3175701305 ps |
| T814 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3161365212 |
|
|
Jun 07 06:22:00 PM PDT 24 |
Jun 07 06:22:08 PM PDT 24 |
1714247154 ps |
| T815 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2175589051 |
|
|
Jun 07 06:25:06 PM PDT 24 |
Jun 07 06:29:36 PM PDT 24 |
8658555554 ps |
| T816 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2727800830 |
|
|
Jun 07 06:21:35 PM PDT 24 |
Jun 07 06:22:44 PM PDT 24 |
10540828569 ps |
| T817 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.4273699492 |
|
|
Jun 07 06:22:00 PM PDT 24 |
Jun 07 06:28:05 PM PDT 24 |
5933794591 ps |
| T818 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1822075069 |
|
|
Jun 07 06:21:04 PM PDT 24 |
Jun 07 06:28:32 PM PDT 24 |
8218755383 ps |
| T819 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3210745749 |
|
|
Jun 07 06:25:24 PM PDT 24 |
Jun 07 06:29:40 PM PDT 24 |
3943247796 ps |
| T820 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1696574887 |
|
|
Jun 07 06:20:57 PM PDT 24 |
Jun 07 06:21:03 PM PDT 24 |
3977461890 ps |
| T821 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3014123946 |
|
|
Jun 07 06:22:31 PM PDT 24 |
Jun 07 06:22:35 PM PDT 24 |
352671883 ps |
| T822 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2999216827 |
|
|
Jun 07 06:21:19 PM PDT 24 |
Jun 07 06:22:35 PM PDT 24 |
1393145990 ps |
| T823 |
/workspace/coverage/default/20.sram_ctrl_regwen.2608186346 |
|
|
Jun 07 06:22:34 PM PDT 24 |
Jun 07 06:29:29 PM PDT 24 |
6418403301 ps |
| T824 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2700882788 |
|
|
Jun 07 06:25:16 PM PDT 24 |
Jun 07 06:25:34 PM PDT 24 |
1217054470 ps |
| T825 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3886849366 |
|
|
Jun 07 06:26:53 PM PDT 24 |
Jun 07 06:32:06 PM PDT 24 |
48414221268 ps |
| T826 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2139288973 |
|
|
Jun 07 06:26:18 PM PDT 24 |
Jun 07 06:31:45 PM PDT 24 |
5177183411 ps |
| T827 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3064778850 |
|
|
Jun 07 06:22:00 PM PDT 24 |
Jun 07 06:25:02 PM PDT 24 |
27248250872 ps |
| T828 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2159569440 |
|
|
Jun 07 06:22:05 PM PDT 24 |
Jun 07 06:45:06 PM PDT 24 |
10191300283 ps |
| T829 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3734170780 |
|
|
Jun 07 06:28:04 PM PDT 24 |
Jun 07 07:00:55 PM PDT 24 |
109609458845 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_alert_test.4214439288 |
|
|
Jun 07 06:21:18 PM PDT 24 |
Jun 07 06:21:19 PM PDT 24 |
31531899 ps |
| T831 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.97521113 |
|
|
Jun 07 06:21:22 PM PDT 24 |
Jun 07 06:22:51 PM PDT 24 |
6218318787 ps |
| T832 |
/workspace/coverage/default/21.sram_ctrl_executable.2497197657 |
|
|
Jun 07 06:23:06 PM PDT 24 |
Jun 07 06:55:41 PM PDT 24 |
190351984721 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2455152288 |
|
|
Jun 07 06:27:11 PM PDT 24 |
Jun 07 06:33:40 PM PDT 24 |
26733174747 ps |
| T834 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4102230451 |
|
|
Jun 07 06:21:03 PM PDT 24 |
Jun 07 06:26:59 PM PDT 24 |
22449168129 ps |
| T835 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.1203728406 |
|
|
Jun 07 06:21:53 PM PDT 24 |
Jun 07 06:24:06 PM PDT 24 |
6111294930 ps |
| T836 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3977406390 |
|
|
Jun 07 06:23:15 PM PDT 24 |
Jun 07 06:23:19 PM PDT 24 |
411348972 ps |
| T837 |
/workspace/coverage/default/18.sram_ctrl_executable.233595150 |
|
|
Jun 07 06:21:55 PM PDT 24 |
Jun 07 07:02:23 PM PDT 24 |
10095809988 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.245656972 |
|
|
Jun 07 06:21:26 PM PDT 24 |
Jun 07 06:39:04 PM PDT 24 |
16854500106 ps |
| T839 |
/workspace/coverage/default/34.sram_ctrl_executable.2396372473 |
|
|
Jun 07 06:26:13 PM PDT 24 |
Jun 07 06:45:42 PM PDT 24 |
347015994760 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1628493464 |
|
|
Jun 07 06:27:08 PM PDT 24 |
Jun 07 06:28:26 PM PDT 24 |
2375268886 ps |
| T841 |
/workspace/coverage/default/13.sram_ctrl_smoke.3725844849 |
|
|
Jun 07 06:21:30 PM PDT 24 |
Jun 07 06:21:51 PM PDT 24 |
1247477884 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3456573322 |
|
|
Jun 07 06:23:15 PM PDT 24 |
Jun 07 06:25:37 PM PDT 24 |
10129108185 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3512780833 |
|
|
Jun 07 06:26:31 PM PDT 24 |
Jun 07 06:29:33 PM PDT 24 |
18290017448 ps |
| T844 |
/workspace/coverage/default/47.sram_ctrl_bijection.2064794857 |
|
|
Jun 07 06:27:37 PM PDT 24 |
Jun 07 06:56:23 PM PDT 24 |
402842483836 ps |
| T845 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1010983380 |
|
|
Jun 07 06:26:18 PM PDT 24 |
Jun 07 06:26:40 PM PDT 24 |
709756329 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.4106627972 |
|
|
Jun 07 06:26:19 PM PDT 24 |
Jun 07 06:26:23 PM PDT 24 |
358328741 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.925189470 |
|
|
Jun 07 06:21:48 PM PDT 24 |
Jun 07 06:23:58 PM PDT 24 |
2061132231 ps |
| T848 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.453726140 |
|
|
Jun 07 06:21:58 PM PDT 24 |
Jun 07 06:24:17 PM PDT 24 |
3323040539 ps |
| T849 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3510780591 |
|
|
Jun 07 06:26:23 PM PDT 24 |
Jun 07 06:26:27 PM PDT 24 |
1130076005 ps |
| T850 |
/workspace/coverage/default/20.sram_ctrl_executable.1236224669 |
|
|
Jun 07 06:22:29 PM PDT 24 |
Jun 07 06:32:11 PM PDT 24 |
17196345438 ps |
| T851 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1432472768 |
|
|
Jun 07 06:27:56 PM PDT 24 |
Jun 07 06:30:10 PM PDT 24 |
7307256451 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3918993539 |
|
|
Jun 07 06:25:42 PM PDT 24 |
Jun 07 06:28:29 PM PDT 24 |
19699131198 ps |
| T853 |
/workspace/coverage/default/2.sram_ctrl_executable.1635913145 |
|
|
Jun 07 06:21:07 PM PDT 24 |
Jun 07 06:38:58 PM PDT 24 |
161570489430 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.1325612521 |
|
|
Jun 07 06:21:11 PM PDT 24 |
Jun 07 06:28:16 PM PDT 24 |
6101211447 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_stress_all.4235921968 |
|
|
Jun 07 06:26:33 PM PDT 24 |
Jun 07 07:14:37 PM PDT 24 |
191375148539 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1861809137 |
|
|
Jun 07 06:21:59 PM PDT 24 |
Jun 07 06:22:00 PM PDT 24 |
34810089 ps |
| T857 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.328155354 |
|
|
Jun 07 06:25:36 PM PDT 24 |
Jun 07 06:28:49 PM PDT 24 |
5082750792 ps |
| T858 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.4118009069 |
|
|
Jun 07 06:25:43 PM PDT 24 |
Jun 07 06:25:55 PM PDT 24 |
1771818130 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_smoke.3848870520 |
|
|
Jun 07 06:26:34 PM PDT 24 |
Jun 07 06:27:00 PM PDT 24 |
1675641355 ps |
| T860 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2738493878 |
|
|
Jun 07 06:27:50 PM PDT 24 |
Jun 07 06:33:33 PM PDT 24 |
33168475542 ps |
| T861 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.60006493 |
|
|
Jun 07 06:26:36 PM PDT 24 |
Jun 07 06:26:40 PM PDT 24 |
346694192 ps |
| T862 |
/workspace/coverage/default/19.sram_ctrl_bijection.4229909257 |
|
|
Jun 07 06:22:00 PM PDT 24 |
Jun 07 06:52:12 PM PDT 24 |
103583288985 ps |
| T863 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.885082879 |
|
|
Jun 07 06:26:29 PM PDT 24 |
Jun 07 06:26:33 PM PDT 24 |
683556383 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2667391605 |
|
|
Jun 07 06:21:46 PM PDT 24 |
Jun 07 06:24:50 PM PDT 24 |
23838807820 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2464325290 |
|
|
Jun 07 06:21:12 PM PDT 24 |
Jun 07 06:21:16 PM PDT 24 |
1768773450 ps |
| T866 |
/workspace/coverage/default/43.sram_ctrl_bijection.2599282553 |
|
|
Jun 07 06:27:06 PM PDT 24 |
Jun 07 06:43:38 PM PDT 24 |
43175588469 ps |
| T867 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3971214163 |
|
|
Jun 07 06:27:36 PM PDT 24 |
Jun 07 06:27:37 PM PDT 24 |
38619627 ps |
| T868 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2418860187 |
|
|
Jun 07 06:26:30 PM PDT 24 |
Jun 07 06:26:34 PM PDT 24 |
1472777454 ps |
| T869 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3514903525 |
|
|
Jun 07 06:21:35 PM PDT 24 |
Jun 07 06:24:20 PM PDT 24 |
14123466940 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_partial_access.452302108 |
|
|
Jun 07 06:25:56 PM PDT 24 |
Jun 07 06:26:22 PM PDT 24 |
3394961662 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.541262574 |
|
|
Jun 07 06:21:33 PM PDT 24 |
Jun 07 06:27:32 PM PDT 24 |
21572472575 ps |
| T872 |
/workspace/coverage/default/45.sram_ctrl_executable.353080572 |
|
|
Jun 07 06:27:26 PM PDT 24 |
Jun 07 06:37:07 PM PDT 24 |
17626881517 ps |
| T873 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3026860863 |
|
|
Jun 07 06:21:42 PM PDT 24 |
Jun 07 06:21:46 PM PDT 24 |
671783999 ps |
| T874 |
/workspace/coverage/default/30.sram_ctrl_bijection.406252188 |
|
|
Jun 07 06:25:43 PM PDT 24 |
Jun 07 06:45:44 PM PDT 24 |
17791849357 ps |
| T875 |
/workspace/coverage/default/49.sram_ctrl_smoke.1490419488 |
|
|
Jun 07 06:27:55 PM PDT 24 |
Jun 07 06:28:03 PM PDT 24 |
1955144264 ps |
| T876 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.4113360024 |
|
|
Jun 07 06:25:51 PM PDT 24 |
Jun 07 06:30:19 PM PDT 24 |
4961156320 ps |
| T877 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.505374785 |
|
|
Jun 07 06:26:40 PM PDT 24 |
Jun 07 06:29:58 PM PDT 24 |
784610348 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_executable.3679436266 |
|
|
Jun 07 06:25:18 PM PDT 24 |
Jun 07 06:32:40 PM PDT 24 |
34326855057 ps |
| T879 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3824973119 |
|
|
Jun 07 06:25:26 PM PDT 24 |
Jun 07 06:32:17 PM PDT 24 |
91436159559 ps |
| T880 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2216419776 |
|
|
Jun 07 06:26:53 PM PDT 24 |
Jun 07 06:26:54 PM PDT 24 |
53994867 ps |
| T881 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3933172162 |
|
|
Jun 07 06:20:57 PM PDT 24 |
Jun 07 06:20:59 PM PDT 24 |
31877193 ps |
| T882 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2464010539 |
|
|
Jun 07 06:25:18 PM PDT 24 |
Jun 07 06:26:28 PM PDT 24 |
3826780158 ps |
| T883 |
/workspace/coverage/default/8.sram_ctrl_executable.3843940349 |
|
|
Jun 07 06:21:26 PM PDT 24 |
Jun 07 06:59:08 PM PDT 24 |
191915283331 ps |
| T884 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2340972303 |
|
|
Jun 07 06:21:12 PM PDT 24 |
Jun 07 06:26:32 PM PDT 24 |
41095658895 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_executable.2789122482 |
|
|
Jun 07 06:27:04 PM PDT 24 |
Jun 07 06:46:41 PM PDT 24 |
40209848120 ps |
| T886 |
/workspace/coverage/default/42.sram_ctrl_smoke.3559536120 |
|
|
Jun 07 06:26:52 PM PDT 24 |
Jun 07 06:27:42 PM PDT 24 |
1380647197 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.668016779 |
|
|
Jun 07 06:24:50 PM PDT 24 |
Jun 07 06:33:21 PM PDT 24 |
92246206418 ps |
| T888 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2544433977 |
|
|
Jun 07 06:26:18 PM PDT 24 |
Jun 07 06:26:22 PM PDT 24 |
729436154 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3062166812 |
|
|
Jun 07 06:21:25 PM PDT 24 |
Jun 07 06:25:26 PM PDT 24 |
4128811560 ps |
| T890 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3266166299 |
|
|
Jun 07 06:21:41 PM PDT 24 |
Jun 07 06:21:56 PM PDT 24 |
4488779313 ps |
| T891 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2976251883 |
|
|
Jun 07 06:21:10 PM PDT 24 |
Jun 07 06:22:37 PM PDT 24 |
3032661620 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4111299436 |
|
|
Jun 07 06:25:49 PM PDT 24 |
Jun 07 06:25:56 PM PDT 24 |
154340691 ps |
| T893 |
/workspace/coverage/default/46.sram_ctrl_regwen.1007922349 |
|
|
Jun 07 06:27:36 PM PDT 24 |
Jun 07 06:33:59 PM PDT 24 |
7518583902 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_stress_all.780740262 |
|
|
Jun 07 06:25:59 PM PDT 24 |
Jun 07 07:45:45 PM PDT 24 |
64598812449 ps |
| T895 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3884389545 |
|
|
Jun 07 06:25:10 PM PDT 24 |
Jun 07 06:25:14 PM PDT 24 |
352080105 ps |
| T896 |
/workspace/coverage/default/7.sram_ctrl_executable.3185421138 |
|
|
Jun 07 06:21:25 PM PDT 24 |
Jun 07 06:37:08 PM PDT 24 |
56648067038 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_executable.1464620431 |
|
|
Jun 07 06:21:13 PM PDT 24 |
Jun 07 06:30:31 PM PDT 24 |
36443558681 ps |
| T898 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1868927413 |
|
|
Jun 07 06:21:40 PM PDT 24 |
Jun 07 06:38:49 PM PDT 24 |
19652097124 ps |
| T899 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1072942103 |
|
|
Jun 07 06:26:59 PM PDT 24 |
Jun 07 06:27:00 PM PDT 24 |
18745605 ps |
| T900 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3580569714 |
|
|
Jun 07 06:21:09 PM PDT 24 |
Jun 07 06:24:35 PM PDT 24 |
5317593084 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4201819535 |
|
|
Jun 07 06:21:01 PM PDT 24 |
Jun 07 06:27:09 PM PDT 24 |
62755644034 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1164680623 |
|
|
Jun 07 06:24:18 PM PDT 24 |
Jun 07 06:28:49 PM PDT 24 |
5588074886 ps |
| T903 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2334702235 |
|
|
Jun 07 06:21:13 PM PDT 24 |
Jun 07 06:24:15 PM PDT 24 |
10444168636 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2214191078 |
|
|
Jun 07 06:25:13 PM PDT 24 |
Jun 07 06:25:31 PM PDT 24 |
2914143478 ps |
| T905 |
/workspace/coverage/default/3.sram_ctrl_regwen.3137765414 |
|
|
Jun 07 06:21:05 PM PDT 24 |
Jun 07 06:25:28 PM PDT 24 |
8063562834 ps |
| T906 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1740429492 |
|
|
Jun 07 06:20:57 PM PDT 24 |
Jun 07 06:21:16 PM PDT 24 |
5116780213 ps |
| T907 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1693779830 |
|
|
Jun 07 06:21:32 PM PDT 24 |
Jun 07 07:58:08 PM PDT 24 |
198307326534 ps |
| T908 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3937107984 |
|
|
Jun 07 06:26:41 PM PDT 24 |
Jun 07 06:29:54 PM PDT 24 |
3194659673 ps |
| T909 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2715288998 |
|
|
Jun 07 06:21:20 PM PDT 24 |
Jun 07 06:21:22 PM PDT 24 |
18180159 ps |
| T910 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2320393265 |
|
|
Jun 07 06:21:02 PM PDT 24 |
Jun 07 06:21:05 PM PDT 24 |
722175319 ps |
| T911 |
/workspace/coverage/default/49.sram_ctrl_regwen.999194203 |
|
|
Jun 07 06:28:02 PM PDT 24 |
Jun 07 06:38:07 PM PDT 24 |
7543288264 ps |
| T912 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3679010628 |
|
|
Jun 07 06:26:25 PM PDT 24 |
Jun 07 06:27:43 PM PDT 24 |
2730060432 ps |
| T913 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3884011420 |
|
|
Jun 07 06:27:34 PM PDT 24 |
Jun 07 06:27:35 PM PDT 24 |
30775149 ps |
| T914 |
/workspace/coverage/default/44.sram_ctrl_regwen.3194963870 |
|
|
Jun 07 06:27:16 PM PDT 24 |
Jun 07 06:34:02 PM PDT 24 |
6036699282 ps |
| T915 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2848819091 |
|
|
Jun 07 06:26:28 PM PDT 24 |
Jun 07 06:29:33 PM PDT 24 |
23176982903 ps |
| T916 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2399600913 |
|
|
Jun 07 06:25:24 PM PDT 24 |
Jun 07 06:28:47 PM PDT 24 |
3663167930 ps |
| T917 |
/workspace/coverage/default/46.sram_ctrl_smoke.3772405925 |
|
|
Jun 07 06:27:31 PM PDT 24 |
Jun 07 06:28:57 PM PDT 24 |
452526829 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3852985072 |
|
|
Jun 07 06:25:16 PM PDT 24 |
Jun 07 06:25:17 PM PDT 24 |
42701266 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3045054703 |
|
|
Jun 07 06:21:00 PM PDT 24 |
Jun 07 06:21:19 PM PDT 24 |
4778733998 ps |
| T920 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3181523334 |
|
|
Jun 07 06:21:06 PM PDT 24 |
Jun 07 06:21:07 PM PDT 24 |
17062663 ps |
| T921 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2874122175 |
|
|
Jun 07 06:23:41 PM PDT 24 |
Jun 07 06:23:47 PM PDT 24 |
695385623 ps |
| T922 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3843827270 |
|
|
Jun 07 06:22:13 PM PDT 24 |
Jun 07 06:39:41 PM PDT 24 |
69209637093 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.116941222 |
|
|
Jun 07 06:21:10 PM PDT 24 |
Jun 07 06:26:14 PM PDT 24 |
11692931230 ps |
| T924 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2172191437 |
|
|
Jun 07 06:20:59 PM PDT 24 |
Jun 07 07:28:50 PM PDT 24 |
818486871804 ps |
| T925 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2808400388 |
|
|
Jun 07 06:25:43 PM PDT 24 |
Jun 07 06:26:07 PM PDT 24 |
2922503507 ps |
| T926 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.404276936 |
|
|
Jun 07 06:21:15 PM PDT 24 |
Jun 07 06:21:21 PM PDT 24 |
2673501390 ps |
| T927 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3797796685 |
|
|
Jun 07 06:21:00 PM PDT 24 |
Jun 07 06:22:05 PM PDT 24 |
3995632378 ps |
| T928 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1370797548 |
|
|
Jun 07 06:27:36 PM PDT 24 |
Jun 07 06:44:49 PM PDT 24 |
10637863425 ps |
| T929 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3276657402 |
|
|
Jun 07 06:25:55 PM PDT 24 |
Jun 07 06:31:59 PM PDT 24 |
26874954953 ps |
| T930 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.762433123 |
|
|
Jun 07 06:25:28 PM PDT 24 |
Jun 07 06:25:36 PM PDT 24 |
2598133695 ps |
| T931 |
/workspace/coverage/default/10.sram_ctrl_alert_test.558498312 |
|
|
Jun 07 06:21:30 PM PDT 24 |
Jun 07 06:21:31 PM PDT 24 |
15679807 ps |
| T932 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.372473713 |
|
|
Jun 07 06:26:17 PM PDT 24 |
Jun 07 06:27:10 PM PDT 24 |
744836413 ps |
| T933 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1332850712 |
|
|
Jun 07 06:21:18 PM PDT 24 |
Jun 07 06:36:27 PM PDT 24 |
16285163665 ps |
| T934 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.682821191 |
|
|
Jun 07 06:21:19 PM PDT 24 |
Jun 07 06:48:48 PM PDT 24 |
13576629972 ps |
| T935 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3747713669 |
|
|
Jun 07 06:24:53 PM PDT 24 |
Jun 07 06:30:51 PM PDT 24 |
18328202170 ps |
| T936 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2873549632 |
|
|
Jun 07 06:25:49 PM PDT 24 |
Jun 07 06:25:59 PM PDT 24 |
1434042910 ps |
| T937 |
/workspace/coverage/default/4.sram_ctrl_regwen.1191203460 |
|
|
Jun 07 06:21:11 PM PDT 24 |
Jun 07 06:33:21 PM PDT 24 |
3787403338 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4081128348 |
|
|
Jun 07 06:18:25 PM PDT 24 |
Jun 07 06:18:26 PM PDT 24 |
17932640 ps |
| T53 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.504715748 |
|
|
Jun 07 06:18:33 PM PDT 24 |
Jun 07 06:18:34 PM PDT 24 |
13685170 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1205582658 |
|
|
Jun 07 06:18:12 PM PDT 24 |
Jun 07 06:18:13 PM PDT 24 |
22701002 ps |
| T55 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1821437437 |
|
|
Jun 07 06:18:32 PM PDT 24 |
Jun 07 06:18:33 PM PDT 24 |
19372907 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3321308573 |
|
|
Jun 07 06:17:56 PM PDT 24 |
Jun 07 06:18:52 PM PDT 24 |
28256115359 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3474775539 |
|
|
Jun 07 06:18:26 PM PDT 24 |
Jun 07 06:18:27 PM PDT 24 |
31433110 ps |
| T938 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2495303093 |
|
|
Jun 07 06:18:15 PM PDT 24 |
Jun 07 06:18:20 PM PDT 24 |
1826724530 ps |
| T45 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4020099681 |
|
|
Jun 07 06:18:15 PM PDT 24 |
Jun 07 06:18:17 PM PDT 24 |
410487884 ps |
| T46 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.923027473 |
|
|
Jun 07 06:18:10 PM PDT 24 |
Jun 07 06:18:11 PM PDT 24 |
189816030 ps |
| T65 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3583645957 |
|
|
Jun 07 06:18:33 PM PDT 24 |
Jun 07 06:18:34 PM PDT 24 |
26481449 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2150396418 |
|
|
Jun 07 06:18:34 PM PDT 24 |
Jun 07 06:18:35 PM PDT 24 |
31687051 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2894169455 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:06 PM PDT 24 |
203536242 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2787768689 |
|
|
Jun 07 06:18:17 PM PDT 24 |
Jun 07 06:18:19 PM PDT 24 |
54812054 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.515849535 |
|
|
Jun 07 06:18:10 PM PDT 24 |
Jun 07 06:18:12 PM PDT 24 |
21668220 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.730349514 |
|
|
Jun 07 06:18:22 PM PDT 24 |
Jun 07 06:18:50 PM PDT 24 |
13736129765 ps |
| T47 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1842138741 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:06 PM PDT 24 |
646335387 ps |
| T939 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1719379373 |
|
|
Jun 07 06:18:24 PM PDT 24 |
Jun 07 06:18:26 PM PDT 24 |
70088689 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4179927488 |
|
|
Jun 07 06:18:27 PM PDT 24 |
Jun 07 06:18:28 PM PDT 24 |
14172544 ps |
| T940 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.525195496 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:08 PM PDT 24 |
1367419874 ps |
| T70 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3522298054 |
|
|
Jun 07 06:17:48 PM PDT 24 |
Jun 07 06:17:50 PM PDT 24 |
338792025 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.16419576 |
|
|
Jun 07 06:17:51 PM PDT 24 |
Jun 07 06:17:52 PM PDT 24 |
33304041 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3441042805 |
|
|
Jun 07 06:18:09 PM PDT 24 |
Jun 07 06:18:13 PM PDT 24 |
544033993 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2619351448 |
|
|
Jun 07 06:18:45 PM PDT 24 |
Jun 07 06:18:50 PM PDT 24 |
1475685444 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.693140092 |
|
|
Jun 07 06:18:35 PM PDT 24 |
Jun 07 06:18:40 PM PDT 24 |
430394749 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.583414495 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:05 PM PDT 24 |
32223297 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.303269652 |
|
|
Jun 07 06:18:29 PM PDT 24 |
Jun 07 06:18:30 PM PDT 24 |
21203080 ps |
| T94 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.62163323 |
|
|
Jun 07 06:18:27 PM PDT 24 |
Jun 07 06:19:21 PM PDT 24 |
14522196352 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2209349578 |
|
|
Jun 07 06:18:02 PM PDT 24 |
Jun 07 06:18:07 PM PDT 24 |
49986717 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1527657011 |
|
|
Jun 07 06:18:16 PM PDT 24 |
Jun 07 06:18:17 PM PDT 24 |
23050417 ps |
| T73 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2467918185 |
|
|
Jun 07 06:17:53 PM PDT 24 |
Jun 07 06:18:21 PM PDT 24 |
3854257481 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1856795651 |
|
|
Jun 07 06:18:36 PM PDT 24 |
Jun 07 06:19:02 PM PDT 24 |
3789592829 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2299388160 |
|
|
Jun 07 06:17:59 PM PDT 24 |
Jun 07 06:18:01 PM PDT 24 |
127868627 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3989624989 |
|
|
Jun 07 06:18:30 PM PDT 24 |
Jun 07 06:18:34 PM PDT 24 |
161632614 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2562896670 |
|
|
Jun 07 06:18:14 PM PDT 24 |
Jun 07 06:18:16 PM PDT 24 |
26901019 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2859057112 |
|
|
Jun 07 06:18:23 PM PDT 24 |
Jun 07 06:18:26 PM PDT 24 |
184818546 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4242256557 |
|
|
Jun 07 06:17:50 PM PDT 24 |
Jun 07 06:17:54 PM PDT 24 |
1369433155 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3754796542 |
|
|
Jun 07 06:17:55 PM PDT 24 |
Jun 07 06:17:59 PM PDT 24 |
348634908 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1395175586 |
|
|
Jun 07 06:18:14 PM PDT 24 |
Jun 07 06:18:19 PM PDT 24 |
366135709 ps |
| T953 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1760180657 |
|
|
Jun 07 06:18:16 PM PDT 24 |
Jun 07 06:18:17 PM PDT 24 |
24104210 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.229213233 |
|
|
Jun 07 06:18:35 PM PDT 24 |
Jun 07 06:18:36 PM PDT 24 |
32628492 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4252285445 |
|
|
Jun 07 06:18:12 PM PDT 24 |
Jun 07 06:18:17 PM PDT 24 |
1479946807 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.682926551 |
|
|
Jun 07 06:18:35 PM PDT 24 |
Jun 07 06:18:36 PM PDT 24 |
12600803 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1103602927 |
|
|
Jun 07 06:18:34 PM PDT 24 |
Jun 07 06:18:36 PM PDT 24 |
1900650617 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.347026028 |
|
|
Jun 07 06:18:44 PM PDT 24 |
Jun 07 06:18:47 PM PDT 24 |
179597565 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.101642488 |
|
|
Jun 07 06:18:13 PM PDT 24 |
Jun 07 06:18:14 PM PDT 24 |
29457196 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3055379989 |
|
|
Jun 07 06:18:51 PM PDT 24 |
Jun 07 06:18:52 PM PDT 24 |
27226754 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.11527588 |
|
|
Jun 07 06:18:14 PM PDT 24 |
Jun 07 06:18:16 PM PDT 24 |
25176433 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.525715830 |
|
|
Jun 07 06:17:54 PM PDT 24 |
Jun 07 06:17:55 PM PDT 24 |
17584284 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4277387492 |
|
|
Jun 07 06:18:32 PM PDT 24 |
Jun 07 06:18:35 PM PDT 24 |
362218472 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.229610744 |
|
|
Jun 07 06:18:45 PM PDT 24 |
Jun 07 06:18:48 PM PDT 24 |
71880621 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2825377845 |
|
|
Jun 07 06:18:24 PM PDT 24 |
Jun 07 06:18:28 PM PDT 24 |
1441083583 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.397595118 |
|
|
Jun 07 06:18:37 PM PDT 24 |
Jun 07 06:18:40 PM PDT 24 |
275613346 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.369813180 |
|
|
Jun 07 06:18:11 PM PDT 24 |
Jun 07 06:18:13 PM PDT 24 |
65839758 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3488451515 |
|
|
Jun 07 06:18:32 PM PDT 24 |
Jun 07 06:18:36 PM PDT 24 |
730697856 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.846057695 |
|
|
Jun 07 06:18:23 PM PDT 24 |
Jun 07 06:18:25 PM PDT 24 |
25344008 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3993435724 |
|
|
Jun 07 06:18:13 PM PDT 24 |
Jun 07 06:18:41 PM PDT 24 |
15342478155 ps |
| T77 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1929065223 |
|
|
Jun 07 06:18:33 PM PDT 24 |
Jun 07 06:19:27 PM PDT 24 |
14374144606 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3618607881 |
|
|
Jun 07 06:18:44 PM PDT 24 |
Jun 07 06:19:39 PM PDT 24 |
7063220770 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2098016918 |
|
|
Jun 07 06:18:36 PM PDT 24 |
Jun 07 06:18:40 PM PDT 24 |
527284305 ps |
| T970 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1223923693 |
|
|
Jun 07 06:18:30 PM PDT 24 |
Jun 07 06:18:34 PM PDT 24 |
687600227 ps |
| T115 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2180383355 |
|
|
Jun 07 06:18:15 PM PDT 24 |
Jun 07 06:18:18 PM PDT 24 |
1726473572 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2898818414 |
|
|
Jun 07 06:18:30 PM PDT 24 |
Jun 07 06:18:34 PM PDT 24 |
1453497425 ps |
| T83 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1748452165 |
|
|
Jun 07 06:18:43 PM PDT 24 |
Jun 07 06:19:15 PM PDT 24 |
7729107748 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.562883858 |
|
|
Jun 07 06:18:18 PM PDT 24 |
Jun 07 06:18:22 PM PDT 24 |
251596997 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4093289885 |
|
|
Jun 07 06:18:35 PM PDT 24 |
Jun 07 06:18:39 PM PDT 24 |
700076548 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1053521490 |
|
|
Jun 07 06:18:31 PM PDT 24 |
Jun 07 06:18:32 PM PDT 24 |
35009741 ps |
| T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.917838671 |
|
|
Jun 07 06:18:01 PM PDT 24 |
Jun 07 06:18:02 PM PDT 24 |
74674968 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3773202182 |
|
|
Jun 07 06:18:23 PM PDT 24 |
Jun 07 06:18:24 PM PDT 24 |
40555883 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.260474394 |
|
|
Jun 07 06:18:33 PM PDT 24 |
Jun 07 06:19:44 PM PDT 24 |
140705121721 ps |
| T977 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1461873403 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:09 PM PDT 24 |
630736335 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.177989685 |
|
|
Jun 07 06:18:12 PM PDT 24 |
Jun 07 06:18:13 PM PDT 24 |
60860342 ps |
| T118 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.535172042 |
|
|
Jun 07 06:18:40 PM PDT 24 |
Jun 07 06:18:42 PM PDT 24 |
853988872 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1876746279 |
|
|
Jun 07 06:18:10 PM PDT 24 |
Jun 07 06:18:11 PM PDT 24 |
74715061 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.195104583 |
|
|
Jun 07 06:18:22 PM PDT 24 |
Jun 07 06:18:27 PM PDT 24 |
1371320779 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3083528981 |
|
|
Jun 07 06:18:43 PM PDT 24 |
Jun 07 06:18:44 PM PDT 24 |
156553329 ps |
| T85 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1490995879 |
|
|
Jun 07 06:18:18 PM PDT 24 |
Jun 07 06:18:47 PM PDT 24 |
16930110242 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2004695084 |
|
|
Jun 07 06:18:43 PM PDT 24 |
Jun 07 06:18:45 PM PDT 24 |
355851096 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4170313496 |
|
|
Jun 07 06:18:51 PM PDT 24 |
Jun 07 06:18:53 PM PDT 24 |
14741079 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2819382345 |
|
|
Jun 07 06:18:33 PM PDT 24 |
Jun 07 06:18:36 PM PDT 24 |
386206479 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3331979101 |
|
|
Jun 07 06:18:36 PM PDT 24 |
Jun 07 06:18:41 PM PDT 24 |
1652662303 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.634936698 |
|
|
Jun 07 06:18:27 PM PDT 24 |
Jun 07 06:18:31 PM PDT 24 |
35811670 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.569326278 |
|
|
Jun 07 06:17:48 PM PDT 24 |
Jun 07 06:17:49 PM PDT 24 |
20970310 ps |
| T985 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3383127884 |
|
|
Jun 07 06:18:25 PM PDT 24 |
Jun 07 06:18:28 PM PDT 24 |
788260158 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3733150736 |
|
|
Jun 07 06:18:19 PM PDT 24 |
Jun 07 06:19:11 PM PDT 24 |
14670453592 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3299407005 |
|
|
Jun 07 06:18:51 PM PDT 24 |
Jun 07 06:18:53 PM PDT 24 |
12437976 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1990322605 |
|
|
Jun 07 06:18:34 PM PDT 24 |
Jun 07 06:18:39 PM PDT 24 |
1436793599 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3469829894 |
|
|
Jun 07 06:18:28 PM PDT 24 |
Jun 07 06:18:29 PM PDT 24 |
18248459 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4030409964 |
|
|
Jun 07 06:18:35 PM PDT 24 |
Jun 07 06:19:06 PM PDT 24 |
13196132337 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1516974415 |
|
|
Jun 07 06:17:56 PM PDT 24 |
Jun 07 06:17:57 PM PDT 24 |
93616080 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3837174366 |
|
|
Jun 07 06:18:23 PM PDT 24 |
Jun 07 06:18:25 PM PDT 24 |
63770173 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1036955911 |
|
|
Jun 07 06:18:44 PM PDT 24 |
Jun 07 06:18:48 PM PDT 24 |
711655838 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2744856031 |
|
|
Jun 07 06:17:48 PM PDT 24 |
Jun 07 06:17:49 PM PDT 24 |
13437945 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3968922862 |
|
|
Jun 07 06:18:22 PM PDT 24 |
Jun 07 06:18:27 PM PDT 24 |
7125628908 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3681016223 |
|
|
Jun 07 06:18:02 PM PDT 24 |
Jun 07 06:18:03 PM PDT 24 |
96936518 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2211506412 |
|
|
Jun 07 06:18:36 PM PDT 24 |
Jun 07 06:18:37 PM PDT 24 |
14336400 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.677074748 |
|
|
Jun 07 06:18:31 PM PDT 24 |
Jun 07 06:19:01 PM PDT 24 |
3701563881 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.88285163 |
|
|
Jun 07 06:17:55 PM PDT 24 |
Jun 07 06:17:58 PM PDT 24 |
663366627 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3750574805 |
|
|
Jun 07 06:17:52 PM PDT 24 |
Jun 07 06:17:57 PM PDT 24 |
127823516 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2167286000 |
|
|
Jun 07 06:18:46 PM PDT 24 |
Jun 07 06:18:47 PM PDT 24 |
13871313 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1963218226 |
|
|
Jun 07 06:18:45 PM PDT 24 |
Jun 07 06:18:48 PM PDT 24 |
162896567 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3240135232 |
|
|
Jun 07 06:18:13 PM PDT 24 |
Jun 07 06:18:16 PM PDT 24 |
245297895 ps |
| T1001 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3387266739 |
|
|
Jun 07 06:18:34 PM PDT 24 |
Jun 07 06:18:39 PM PDT 24 |
4911258546 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3903847110 |
|
|
Jun 07 06:18:18 PM PDT 24 |
Jun 07 06:18:19 PM PDT 24 |
33362142 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.830877292 |
|
|
Jun 07 06:18:43 PM PDT 24 |
Jun 07 06:19:12 PM PDT 24 |
3747734876 ps |
| T1004 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3366334291 |
|
|
Jun 07 06:18:25 PM PDT 24 |
Jun 07 06:18:56 PM PDT 24 |
7689524060 ps |
| T116 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1441804382 |
|
|
Jun 07 06:18:04 PM PDT 24 |
Jun 07 06:18:06 PM PDT 24 |
650703702 ps |