Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	328179876	1			T1	19828		T2	15824		T3	5190
instr_valid_dis	284171235	1			T1	19828		T2	15824		T3	5190
instr_en	29166811	1			T4	26228		T25	21600		T14	98

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14851140	1			T4	111210		T5	96972		T25	77190
sram_ifetch_valid_disable	292192218	1			T1	19828		T2	15824		T3	5190
sram_ifetch_enable	21136518	1			T4	210046		T5	94508		T14	196384

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	328179876	1			T1	19828		T2	15824		T3	5190
hw_debug_en_valid_off	283021362	1			T1	19828		T2	15824		T3	5190
hw_debug_en_on	24763032	1			T4	295998		T5	142048		T25	77190

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	292192218	1			T1	19828		T2	15824		T3	5190
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	268828513	1			T1	19828		T2	15824		T3	5190
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	17793923	1			T4	26228		T25	21600		T28	175898
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4466380	1			T4	28724		T5	27168		T124	33544
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1908864	1			T4	28724		T5	27168		T19	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1749190	1			T19	53584		T20	27478		T120	4962
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4996984	1			T4	43280		T5	41636		T25	77190
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2656172	1			T4	43280		T5	41636		T25	77190
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1667484	1			T28	21596		T33	9762		T19	14002
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10881458	1			T4	111560		T5	19418		T14	18518
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6395472	1			T4	111560		T5	19418		T28	2972
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3308642	1			T28	69334		T124	4556		T119	338

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7144728	1			T28	3108		T124	18692		T33	41320
lc_exec_en	8884590	1			T4	141158		T5	80994		T14	11958
valid_exec_dis	280406742	1			T1	19828		T2	15824		T3	5190
invalid_exec_dis	35987658	1			T4	321256		T5	191480		T25	77190