Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	133692212	1			T1	9032		T2	7176		T3	183
triple_byte_access	2851984	1			T1	190		T2	142		T3	5
halfword_access	4374081	1			T1	267		T2	215		T3	8
byte_access	6114495	1			T1	349		T2	298		T3	9
zero_access	1851018	1			T1	76		T2	81		T3	2

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74206388

1

T1

4913

T2

3955

T3

93

auto[1]

74677402

1

T1

5001

T2

3957

T3

114

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	66469413	1			T1	4481		T2	3607		T3	80
auto[0]	triple_byte_access	1360325	1			T1	92		T2	70		T3	3
auto[0]	halfword_access	2136787	1			T1	141		T2	110		T3	7
auto[0]	byte_access	3133503	1			T1	168		T2	128		T3	3
auto[0]	zero_access	1106360	1			T1	31		T2	40		T4	1248
auto[1]	word_access	67222799	1			T1	4551		T2	3569		T3	103
auto[1]	triple_byte_access	1491659	1			T1	98		T2	72		T3	2
auto[1]	halfword_access	2237294	1			T1	126		T2	105		T3	1
auto[1]	byte_access	2980992	1			T1	181		T2	170		T3	6
auto[1]	zero_access	744658	1			T1	45		T2	41		T3	2