| T793 |
/workspace/coverage/default/40.sram_ctrl_regwen.954360983 |
|
|
Jun 11 12:52:25 PM PDT 24 |
Jun 11 01:03:10 PM PDT 24 |
18321992732 ps |
| T794 |
/workspace/coverage/default/37.sram_ctrl_alert_test.640112973 |
|
|
Jun 11 12:52:06 PM PDT 24 |
Jun 11 12:52:08 PM PDT 24 |
14453384 ps |
| T795 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.65730950 |
|
|
Jun 11 12:52:29 PM PDT 24 |
Jun 11 01:24:48 PM PDT 24 |
56397009711 ps |
| T796 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.121590740 |
|
|
Jun 11 12:52:24 PM PDT 24 |
Jun 11 12:56:51 PM PDT 24 |
16412169912 ps |
| T797 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2891032797 |
|
|
Jun 11 12:51:02 PM PDT 24 |
Jun 11 12:52:22 PM PDT 24 |
5540955591 ps |
| T798 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.987554408 |
|
|
Jun 11 12:51:49 PM PDT 24 |
Jun 11 12:54:16 PM PDT 24 |
777359746 ps |
| T105 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3800878833 |
|
|
Jun 11 12:51:05 PM PDT 24 |
Jun 11 12:53:08 PM PDT 24 |
5964584228 ps |
| T799 |
/workspace/coverage/default/43.sram_ctrl_executable.2272174744 |
|
|
Jun 11 12:52:37 PM PDT 24 |
Jun 11 01:02:40 PM PDT 24 |
20696710284 ps |
| T800 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2285227394 |
|
|
Jun 11 12:52:13 PM PDT 24 |
Jun 11 12:52:21 PM PDT 24 |
705205233 ps |
| T801 |
/workspace/coverage/default/0.sram_ctrl_partial_access.2018485254 |
|
|
Jun 11 12:50:24 PM PDT 24 |
Jun 11 12:51:31 PM PDT 24 |
1017868071 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.948886925 |
|
|
Jun 11 12:51:36 PM PDT 24 |
Jun 11 12:51:45 PM PDT 24 |
2479029977 ps |
| T803 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.388785386 |
|
|
Jun 11 12:51:29 PM PDT 24 |
Jun 11 12:52:53 PM PDT 24 |
9429689955 ps |
| T804 |
/workspace/coverage/default/12.sram_ctrl_stress_all.596497431 |
|
|
Jun 11 12:50:57 PM PDT 24 |
Jun 11 02:04:15 PM PDT 24 |
309714310282 ps |
| T805 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2369489929 |
|
|
Jun 11 12:50:42 PM PDT 24 |
Jun 11 12:50:45 PM PDT 24 |
27461949 ps |
| T806 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1306799988 |
|
|
Jun 11 12:50:54 PM PDT 24 |
Jun 11 01:16:00 PM PDT 24 |
14901262671 ps |
| T807 |
/workspace/coverage/default/12.sram_ctrl_executable.4016078769 |
|
|
Jun 11 12:50:50 PM PDT 24 |
Jun 11 01:10:02 PM PDT 24 |
30298184709 ps |
| T808 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.4045665683 |
|
|
Jun 11 12:51:39 PM PDT 24 |
Jun 11 12:54:09 PM PDT 24 |
3815962263 ps |
| T809 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1024561991 |
|
|
Jun 11 12:51:42 PM PDT 24 |
Jun 11 12:54:03 PM PDT 24 |
3134687033 ps |
| T810 |
/workspace/coverage/default/36.sram_ctrl_bijection.1257729187 |
|
|
Jun 11 12:51:52 PM PDT 24 |
Jun 11 01:41:07 PM PDT 24 |
352007209391 ps |
| T811 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3857800765 |
|
|
Jun 11 12:51:00 PM PDT 24 |
Jun 11 12:51:09 PM PDT 24 |
2660817703 ps |
| T812 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3375097557 |
|
|
Jun 11 12:52:59 PM PDT 24 |
Jun 11 12:53:00 PM PDT 24 |
14832858 ps |
| T813 |
/workspace/coverage/default/10.sram_ctrl_regwen.3195026051 |
|
|
Jun 11 12:50:53 PM PDT 24 |
Jun 11 01:03:57 PM PDT 24 |
6191075731 ps |
| T814 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3981874102 |
|
|
Jun 11 12:50:59 PM PDT 24 |
Jun 11 12:51:35 PM PDT 24 |
902099190 ps |
| T815 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3056911862 |
|
|
Jun 11 12:51:37 PM PDT 24 |
Jun 11 12:59:49 PM PDT 24 |
59828644208 ps |
| T816 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1051349795 |
|
|
Jun 11 12:50:49 PM PDT 24 |
Jun 11 12:55:04 PM PDT 24 |
51677601049 ps |
| T817 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.180805836 |
|
|
Jun 11 12:52:02 PM PDT 24 |
Jun 11 12:54:23 PM PDT 24 |
5355920378 ps |
| T818 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.143647838 |
|
|
Jun 11 12:52:34 PM PDT 24 |
Jun 11 12:56:54 PM PDT 24 |
16422115950 ps |
| T819 |
/workspace/coverage/default/1.sram_ctrl_alert_test.27893575 |
|
|
Jun 11 12:50:40 PM PDT 24 |
Jun 11 12:50:42 PM PDT 24 |
38733036 ps |
| T820 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2852625814 |
|
|
Jun 11 12:51:02 PM PDT 24 |
Jun 11 01:28:25 PM PDT 24 |
44299276276 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2978148441 |
|
|
Jun 11 12:51:39 PM PDT 24 |
Jun 11 12:52:18 PM PDT 24 |
5621310020 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2680076946 |
|
|
Jun 11 12:51:31 PM PDT 24 |
Jun 11 02:40:10 PM PDT 24 |
245595994375 ps |
| T823 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.794326508 |
|
|
Jun 11 12:50:54 PM PDT 24 |
Jun 11 12:51:01 PM PDT 24 |
939356991 ps |
| T824 |
/workspace/coverage/default/27.sram_ctrl_regwen.4156255739 |
|
|
Jun 11 12:51:34 PM PDT 24 |
Jun 11 12:54:51 PM PDT 24 |
2508485246 ps |
| T825 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3798056215 |
|
|
Jun 11 12:51:40 PM PDT 24 |
Jun 11 12:52:05 PM PDT 24 |
2296157243 ps |
| T826 |
/workspace/coverage/default/40.sram_ctrl_smoke.645176896 |
|
|
Jun 11 12:52:15 PM PDT 24 |
Jun 11 12:52:27 PM PDT 24 |
817367422 ps |
| T827 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3527242076 |
|
|
Jun 11 12:50:55 PM PDT 24 |
Jun 11 01:11:47 PM PDT 24 |
16639327656 ps |
| T828 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2066174834 |
|
|
Jun 11 12:52:48 PM PDT 24 |
Jun 11 12:54:56 PM PDT 24 |
6836834728 ps |
| T829 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.4216273202 |
|
|
Jun 11 12:51:31 PM PDT 24 |
Jun 11 01:00:15 PM PDT 24 |
40896150880 ps |
| T830 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3948384538 |
|
|
Jun 11 12:50:42 PM PDT 24 |
Jun 11 12:57:27 PM PDT 24 |
21499232849 ps |
| T831 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.859149946 |
|
|
Jun 11 12:51:56 PM PDT 24 |
Jun 11 12:52:27 PM PDT 24 |
27532241692 ps |
| T832 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3236672602 |
|
|
Jun 11 12:53:09 PM PDT 24 |
Jun 11 02:56:15 PM PDT 24 |
254554233451 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.355043696 |
|
|
Jun 11 12:53:21 PM PDT 24 |
Jun 11 12:55:27 PM PDT 24 |
5498032562 ps |
| T834 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2009314671 |
|
|
Jun 11 12:51:33 PM PDT 24 |
Jun 11 12:52:25 PM PDT 24 |
537790808 ps |
| T835 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3511170393 |
|
|
Jun 11 12:51:46 PM PDT 24 |
Jun 11 12:52:01 PM PDT 24 |
1370284043 ps |
| T836 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1516650794 |
|
|
Jun 11 12:51:55 PM PDT 24 |
Jun 11 12:54:07 PM PDT 24 |
4123320447 ps |
| T837 |
/workspace/coverage/default/48.sram_ctrl_regwen.4213827881 |
|
|
Jun 11 12:53:08 PM PDT 24 |
Jun 11 01:06:06 PM PDT 24 |
6714622399 ps |
| T838 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3128051494 |
|
|
Jun 11 12:51:20 PM PDT 24 |
Jun 11 12:53:03 PM PDT 24 |
3076273120 ps |
| T839 |
/workspace/coverage/default/38.sram_ctrl_smoke.839888529 |
|
|
Jun 11 12:52:02 PM PDT 24 |
Jun 11 12:52:36 PM PDT 24 |
973218238 ps |
| T840 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2431879034 |
|
|
Jun 11 12:51:21 PM PDT 24 |
Jun 11 12:58:40 PM PDT 24 |
69438937439 ps |
| T841 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2328009474 |
|
|
Jun 11 12:51:49 PM PDT 24 |
Jun 11 12:51:50 PM PDT 24 |
30271287 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.558970266 |
|
|
Jun 11 12:51:21 PM PDT 24 |
Jun 11 12:58:36 PM PDT 24 |
10172722967 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4055473905 |
|
|
Jun 11 12:51:42 PM PDT 24 |
Jun 11 12:56:55 PM PDT 24 |
50843346920 ps |
| T844 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3426559434 |
|
|
Jun 11 12:50:53 PM PDT 24 |
Jun 11 12:51:37 PM PDT 24 |
23097339501 ps |
| T845 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3552351915 |
|
|
Jun 11 12:52:45 PM PDT 24 |
Jun 11 12:53:56 PM PDT 24 |
1297114661 ps |
| T846 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3451342594 |
|
|
Jun 11 12:50:59 PM PDT 24 |
Jun 11 12:55:00 PM PDT 24 |
4004087460 ps |
| T847 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2163095980 |
|
|
Jun 11 12:50:56 PM PDT 24 |
Jun 11 12:53:27 PM PDT 24 |
24216822131 ps |
| T848 |
/workspace/coverage/default/49.sram_ctrl_executable.2101638956 |
|
|
Jun 11 12:53:22 PM PDT 24 |
Jun 11 01:10:02 PM PDT 24 |
70419346830 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1472429413 |
|
|
Jun 11 12:51:22 PM PDT 24 |
Jun 11 01:04:41 PM PDT 24 |
13902280701 ps |
| T850 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3390850190 |
|
|
Jun 11 12:51:08 PM PDT 24 |
Jun 11 01:00:55 PM PDT 24 |
8484848891 ps |
| T851 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3052143088 |
|
|
Jun 11 12:51:49 PM PDT 24 |
Jun 11 12:51:57 PM PDT 24 |
1409509824 ps |
| T852 |
/workspace/coverage/default/39.sram_ctrl_regwen.2976791658 |
|
|
Jun 11 12:52:15 PM PDT 24 |
Jun 11 01:13:36 PM PDT 24 |
4555828549 ps |
| T853 |
/workspace/coverage/default/40.sram_ctrl_partial_access.826851615 |
|
|
Jun 11 12:52:14 PM PDT 24 |
Jun 11 12:52:32 PM PDT 24 |
1057498370 ps |
| T854 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.25582688 |
|
|
Jun 11 12:51:47 PM PDT 24 |
Jun 11 01:14:18 PM PDT 24 |
60962370068 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.420273927 |
|
|
Jun 11 12:50:46 PM PDT 24 |
Jun 11 12:53:43 PM PDT 24 |
18716816157 ps |
| T856 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3482970404 |
|
|
Jun 11 12:51:21 PM PDT 24 |
Jun 11 01:41:02 PM PDT 24 |
116779102510 ps |
| T857 |
/workspace/coverage/default/17.sram_ctrl_stress_all.903326581 |
|
|
Jun 11 12:50:57 PM PDT 24 |
Jun 11 01:07:09 PM PDT 24 |
27050927697 ps |
| T858 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.898847113 |
|
|
Jun 11 12:52:59 PM PDT 24 |
Jun 11 12:54:27 PM PDT 24 |
1357010062 ps |
| T859 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1971085529 |
|
|
Jun 11 12:52:01 PM PDT 24 |
Jun 11 12:52:05 PM PDT 24 |
32937963 ps |
| T860 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2588750091 |
|
|
Jun 11 12:50:57 PM PDT 24 |
Jun 11 12:51:35 PM PDT 24 |
1463062363 ps |
| T861 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2612867585 |
|
|
Jun 11 12:51:57 PM PDT 24 |
Jun 11 12:53:07 PM PDT 24 |
2704977243 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_executable.1256689899 |
|
|
Jun 11 12:52:47 PM PDT 24 |
Jun 11 01:13:20 PM PDT 24 |
12821801076 ps |
| T863 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2384846003 |
|
|
Jun 11 12:51:14 PM PDT 24 |
Jun 11 12:51:47 PM PDT 24 |
2989547477 ps |
| T864 |
/workspace/coverage/default/20.sram_ctrl_bijection.4084618958 |
|
|
Jun 11 12:51:13 PM PDT 24 |
Jun 11 01:14:01 PM PDT 24 |
221397360799 ps |
| T865 |
/workspace/coverage/default/23.sram_ctrl_partial_access.744191274 |
|
|
Jun 11 12:51:24 PM PDT 24 |
Jun 11 12:52:42 PM PDT 24 |
1174057279 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_executable.4061795890 |
|
|
Jun 11 12:51:25 PM PDT 24 |
Jun 11 12:51:57 PM PDT 24 |
8336981387 ps |
| T867 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3192198953 |
|
|
Jun 11 12:53:10 PM PDT 24 |
Jun 11 12:56:51 PM PDT 24 |
11966636341 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_executable.829338647 |
|
|
Jun 11 12:51:25 PM PDT 24 |
Jun 11 01:29:02 PM PDT 24 |
177775106517 ps |
| T869 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3482286382 |
|
|
Jun 11 12:52:26 PM PDT 24 |
Jun 11 12:53:53 PM PDT 24 |
8700732141 ps |
| T870 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.510180229 |
|
|
Jun 11 12:50:55 PM PDT 24 |
Jun 11 12:51:23 PM PDT 24 |
1460143347 ps |
| T871 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2236076434 |
|
|
Jun 11 12:51:23 PM PDT 24 |
Jun 11 01:09:30 PM PDT 24 |
13220625830 ps |
| T872 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2486003067 |
|
|
Jun 11 12:52:25 PM PDT 24 |
Jun 11 01:25:32 PM PDT 24 |
67752252707 ps |
| T873 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3222060282 |
|
|
Jun 11 12:50:31 PM PDT 24 |
Jun 11 12:50:37 PM PDT 24 |
709379133 ps |
| T874 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1979762563 |
|
|
Jun 11 12:52:02 PM PDT 24 |
Jun 11 01:09:49 PM PDT 24 |
52313299419 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3669965109 |
|
|
Jun 11 12:51:10 PM PDT 24 |
Jun 11 12:51:59 PM PDT 24 |
35991383042 ps |
| T876 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1138842123 |
|
|
Jun 11 12:50:51 PM PDT 24 |
Jun 11 12:51:12 PM PDT 24 |
1576586504 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1115370281 |
|
|
Jun 11 12:51:42 PM PDT 24 |
Jun 11 12:58:45 PM PDT 24 |
75974088175 ps |
| T878 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2544805705 |
|
|
Jun 11 12:50:49 PM PDT 24 |
Jun 11 01:07:53 PM PDT 24 |
16106765405 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1377794011 |
|
|
Jun 11 12:50:59 PM PDT 24 |
Jun 11 12:52:18 PM PDT 24 |
3212261441 ps |
| T880 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.692893446 |
|
|
Jun 11 12:50:20 PM PDT 24 |
Jun 11 12:53:57 PM PDT 24 |
2784710168 ps |
| T881 |
/workspace/coverage/default/13.sram_ctrl_bijection.3979677635 |
|
|
Jun 11 12:51:01 PM PDT 24 |
Jun 11 01:29:42 PM PDT 24 |
397428198298 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1607154173 |
|
|
Jun 11 12:51:42 PM PDT 24 |
Jun 11 12:54:31 PM PDT 24 |
9267852528 ps |
| T883 |
/workspace/coverage/default/34.sram_ctrl_executable.4208676360 |
|
|
Jun 11 12:51:48 PM PDT 24 |
Jun 11 01:08:51 PM PDT 24 |
32729153403 ps |
| T884 |
/workspace/coverage/default/32.sram_ctrl_regwen.3905170533 |
|
|
Jun 11 12:51:37 PM PDT 24 |
Jun 11 01:14:01 PM PDT 24 |
3142752138 ps |
| T885 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.506058360 |
|
|
Jun 11 12:52:24 PM PDT 24 |
Jun 11 12:52:28 PM PDT 24 |
347949929 ps |
| T886 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2797823572 |
|
|
Jun 11 12:52:24 PM PDT 24 |
Jun 11 12:52:35 PM PDT 24 |
3239050421 ps |
| T887 |
/workspace/coverage/default/29.sram_ctrl_stress_all.383589009 |
|
|
Jun 11 12:51:34 PM PDT 24 |
Jun 11 02:14:04 PM PDT 24 |
1999788099412 ps |
| T888 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3980977815 |
|
|
Jun 11 12:51:19 PM PDT 24 |
Jun 11 12:51:21 PM PDT 24 |
16126757 ps |
| T889 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3251996141 |
|
|
Jun 11 12:52:49 PM PDT 24 |
Jun 11 01:00:45 PM PDT 24 |
16156688246 ps |
| T890 |
/workspace/coverage/default/1.sram_ctrl_regwen.4191988681 |
|
|
Jun 11 12:50:34 PM PDT 24 |
Jun 11 12:56:53 PM PDT 24 |
2229314611 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_executable.1665505718 |
|
|
Jun 11 12:50:32 PM PDT 24 |
Jun 11 12:52:16 PM PDT 24 |
3388797451 ps |
| T892 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2252557285 |
|
|
Jun 11 12:52:58 PM PDT 24 |
Jun 11 12:53:27 PM PDT 24 |
1797691250 ps |
| T893 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.68104865 |
|
|
Jun 11 12:51:22 PM PDT 24 |
Jun 11 12:52:36 PM PDT 24 |
39201285673 ps |
| T894 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1851195658 |
|
|
Jun 11 12:51:58 PM PDT 24 |
Jun 11 12:53:27 PM PDT 24 |
3367121735 ps |
| T895 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4053151570 |
|
|
Jun 11 12:50:51 PM PDT 24 |
Jun 11 12:53:34 PM PDT 24 |
6305399510 ps |
| T896 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.418648546 |
|
|
Jun 11 12:52:58 PM PDT 24 |
Jun 11 12:55:12 PM PDT 24 |
17955455872 ps |
| T897 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1543607110 |
|
|
Jun 11 12:51:26 PM PDT 24 |
Jun 11 12:52:00 PM PDT 24 |
1167879863 ps |
| T898 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.287593391 |
|
|
Jun 11 12:51:03 PM PDT 24 |
Jun 11 12:51:08 PM PDT 24 |
1613090521 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_bijection.822115835 |
|
|
Jun 11 12:51:49 PM PDT 24 |
Jun 11 01:27:32 PM PDT 24 |
29178680880 ps |
| T900 |
/workspace/coverage/default/7.sram_ctrl_bijection.1046609599 |
|
|
Jun 11 12:50:50 PM PDT 24 |
Jun 11 01:26:30 PM PDT 24 |
253542619758 ps |
| T901 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3204391635 |
|
|
Jun 11 12:50:57 PM PDT 24 |
Jun 11 12:51:46 PM PDT 24 |
8320116097 ps |
| T902 |
/workspace/coverage/default/30.sram_ctrl_regwen.1703682343 |
|
|
Jun 11 12:51:35 PM PDT 24 |
Jun 11 01:07:05 PM PDT 24 |
41859684671 ps |
| T903 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3892927377 |
|
|
Jun 11 12:51:55 PM PDT 24 |
Jun 11 12:53:07 PM PDT 24 |
3660315912 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.400096683 |
|
|
Jun 11 12:51:22 PM PDT 24 |
Jun 11 12:56:00 PM PDT 24 |
4197558499 ps |
| T905 |
/workspace/coverage/default/11.sram_ctrl_smoke.851090644 |
|
|
Jun 11 12:50:56 PM PDT 24 |
Jun 11 12:51:16 PM PDT 24 |
1301255791 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3623984837 |
|
|
Jun 11 12:51:28 PM PDT 24 |
Jun 11 01:08:03 PM PDT 24 |
17657702706 ps |
| T907 |
/workspace/coverage/default/15.sram_ctrl_regwen.1563069038 |
|
|
Jun 11 12:51:06 PM PDT 24 |
Jun 11 01:00:52 PM PDT 24 |
4727198685 ps |
| T908 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3272830514 |
|
|
Jun 11 12:51:48 PM PDT 24 |
Jun 11 12:52:02 PM PDT 24 |
701221245 ps |
| T909 |
/workspace/coverage/default/49.sram_ctrl_smoke.2354282699 |
|
|
Jun 11 12:53:08 PM PDT 24 |
Jun 11 12:53:27 PM PDT 24 |
2226276886 ps |
| T910 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2233114964 |
|
|
Jun 11 12:52:27 PM PDT 24 |
Jun 11 12:57:05 PM PDT 24 |
10533318802 ps |
| T911 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3292312302 |
|
|
Jun 11 12:51:25 PM PDT 24 |
Jun 11 12:58:03 PM PDT 24 |
129980086062 ps |
| T912 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3084939702 |
|
|
Jun 11 12:50:59 PM PDT 24 |
Jun 11 12:51:26 PM PDT 24 |
5480334955 ps |
| T913 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3902816716 |
|
|
Jun 11 12:50:40 PM PDT 24 |
Jun 11 12:53:08 PM PDT 24 |
2646557297 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.4016108767 |
|
|
Jun 11 12:50:44 PM PDT 24 |
Jun 11 12:51:55 PM PDT 24 |
747580092 ps |
| T915 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3529149683 |
|
|
Jun 11 12:51:36 PM PDT 24 |
Jun 11 12:52:44 PM PDT 24 |
3882028838 ps |
| T916 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1022765816 |
|
|
Jun 11 12:52:03 PM PDT 24 |
Jun 11 12:54:53 PM PDT 24 |
17351329567 ps |
| T917 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2420254292 |
|
|
Jun 11 12:51:16 PM PDT 24 |
Jun 11 12:52:50 PM PDT 24 |
2333275159 ps |
| T918 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2586829221 |
|
|
Jun 11 12:51:33 PM PDT 24 |
Jun 11 12:52:32 PM PDT 24 |
776208090 ps |
| T919 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3378772871 |
|
|
Jun 11 12:52:59 PM PDT 24 |
Jun 11 12:53:10 PM PDT 24 |
835125674 ps |
| T920 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3084837652 |
|
|
Jun 11 12:52:27 PM PDT 24 |
Jun 11 12:52:36 PM PDT 24 |
1405470652 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2923265147 |
|
|
Jun 11 12:51:00 PM PDT 24 |
Jun 11 12:51:10 PM PDT 24 |
456888114 ps |
| T922 |
/workspace/coverage/default/37.sram_ctrl_smoke.2054792630 |
|
|
Jun 11 12:52:03 PM PDT 24 |
Jun 11 12:54:24 PM PDT 24 |
5344054620 ps |
| T923 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4049507727 |
|
|
Jun 11 12:50:48 PM PDT 24 |
Jun 11 12:56:43 PM PDT 24 |
17428395898 ps |
| T924 |
/workspace/coverage/default/38.sram_ctrl_partial_access.4146412786 |
|
|
Jun 11 12:52:05 PM PDT 24 |
Jun 11 12:52:19 PM PDT 24 |
810606876 ps |
| T925 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1780725945 |
|
|
Jun 11 12:51:18 PM PDT 24 |
Jun 11 12:52:52 PM PDT 24 |
50030632388 ps |
| T926 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1276965743 |
|
|
Jun 11 12:52:35 PM PDT 24 |
Jun 11 12:52:55 PM PDT 24 |
544341257 ps |
| T927 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3504258830 |
|
|
Jun 11 12:51:41 PM PDT 24 |
Jun 11 01:06:45 PM PDT 24 |
23947774230 ps |
| T928 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3054271815 |
|
|
Jun 11 12:51:46 PM PDT 24 |
Jun 11 12:53:06 PM PDT 24 |
2409005738 ps |
| T929 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1191310415 |
|
|
Jun 11 12:52:25 PM PDT 24 |
Jun 11 12:52:27 PM PDT 24 |
35051457 ps |
| T930 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.55788732 |
|
|
Jun 11 12:50:48 PM PDT 24 |
Jun 11 12:57:12 PM PDT 24 |
17674415842 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_executable.820382024 |
|
|
Jun 11 12:50:32 PM PDT 24 |
Jun 11 12:57:45 PM PDT 24 |
5491167322 ps |
| T932 |
/workspace/coverage/default/0.sram_ctrl_smoke.2126031234 |
|
|
Jun 11 12:50:27 PM PDT 24 |
Jun 11 12:50:49 PM PDT 24 |
1484732765 ps |
| T933 |
/workspace/coverage/default/29.sram_ctrl_regwen.2799332987 |
|
|
Jun 11 12:51:31 PM PDT 24 |
Jun 11 12:56:11 PM PDT 24 |
9123000859 ps |
| T934 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1386968340 |
|
|
Jun 11 12:50:55 PM PDT 24 |
Jun 11 12:51:55 PM PDT 24 |
3129366115 ps |
| T935 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1362002137 |
|
|
Jun 11 12:51:17 PM PDT 24 |
Jun 11 12:53:54 PM PDT 24 |
3042750424 ps |
| T55 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2657383243 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:33 PM PDT 24 |
11538405 ps |
| T56 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.92819661 |
|
|
Jun 11 12:22:40 PM PDT 24 |
Jun 11 12:22:43 PM PDT 24 |
16798556 ps |
| T52 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2978980431 |
|
|
Jun 11 12:21:26 PM PDT 24 |
Jun 11 12:21:28 PM PDT 24 |
77639471 ps |
| T88 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.197017396 |
|
|
Jun 11 12:22:53 PM PDT 24 |
Jun 11 12:22:56 PM PDT 24 |
32818341 ps |
| T63 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3808482740 |
|
|
Jun 11 12:23:39 PM PDT 24 |
Jun 11 12:23:43 PM PDT 24 |
17191241 ps |
| T936 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2437032482 |
|
|
Jun 11 12:20:26 PM PDT 24 |
Jun 11 12:20:31 PM PDT 24 |
156937255 ps |
| T53 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1230778904 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:35 PM PDT 24 |
136623321 ps |
| T937 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3576989591 |
|
|
Jun 11 12:23:22 PM PDT 24 |
Jun 11 12:23:29 PM PDT 24 |
114398093 ps |
| T64 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1233890416 |
|
|
Jun 11 12:22:44 PM PDT 24 |
Jun 11 12:22:47 PM PDT 24 |
20820987 ps |
| T938 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4180283666 |
|
|
Jun 11 12:22:57 PM PDT 24 |
Jun 11 12:23:06 PM PDT 24 |
1992062407 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2364568567 |
|
|
Jun 11 12:18:03 PM PDT 24 |
Jun 11 12:18:04 PM PDT 24 |
67360541 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1457162303 |
|
|
Jun 11 12:19:53 PM PDT 24 |
Jun 11 12:20:25 PM PDT 24 |
13683032525 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2037590078 |
|
|
Jun 11 12:23:24 PM PDT 24 |
Jun 11 12:24:19 PM PDT 24 |
9725070726 ps |
| T91 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.366486741 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:23:02 PM PDT 24 |
7533356251 ps |
| T66 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2078506609 |
|
|
Jun 11 12:23:24 PM PDT 24 |
Jun 11 12:23:58 PM PDT 24 |
14751912614 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3311978794 |
|
|
Jun 11 12:19:53 PM PDT 24 |
Jun 11 12:19:58 PM PDT 24 |
61167946 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.776824123 |
|
|
Jun 11 12:22:25 PM PDT 24 |
Jun 11 12:22:27 PM PDT 24 |
16226615 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1166171486 |
|
|
Jun 11 12:22:25 PM PDT 24 |
Jun 11 12:22:54 PM PDT 24 |
7555553621 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3637655703 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:34 PM PDT 24 |
48084157 ps |
| T54 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2004738100 |
|
|
Jun 11 12:22:58 PM PDT 24 |
Jun 11 12:23:05 PM PDT 24 |
602759360 ps |
| T112 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2707860028 |
|
|
Jun 11 12:23:29 PM PDT 24 |
Jun 11 12:23:36 PM PDT 24 |
186805996 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2721123743 |
|
|
Jun 11 12:19:19 PM PDT 24 |
Jun 11 12:19:23 PM PDT 24 |
391253495 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1491922825 |
|
|
Jun 11 12:23:07 PM PDT 24 |
Jun 11 12:23:13 PM PDT 24 |
1749520498 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3071893531 |
|
|
Jun 11 12:18:38 PM PDT 24 |
Jun 11 12:18:44 PM PDT 24 |
527841787 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.915510256 |
|
|
Jun 11 12:23:46 PM PDT 24 |
Jun 11 12:23:58 PM PDT 24 |
711205896 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.761637821 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:35 PM PDT 24 |
288791890 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3933195642 |
|
|
Jun 11 12:22:10 PM PDT 24 |
Jun 11 12:22:13 PM PDT 24 |
39971335 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.131730779 |
|
|
Jun 11 12:19:50 PM PDT 24 |
Jun 11 12:19:52 PM PDT 24 |
17205332 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2791085218 |
|
|
Jun 11 12:18:34 PM PDT 24 |
Jun 11 12:18:36 PM PDT 24 |
39476635 ps |
| T71 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1784789376 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:23:27 PM PDT 24 |
31951957611 ps |
| T113 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1453116310 |
|
|
Jun 11 12:23:39 PM PDT 24 |
Jun 11 12:23:44 PM PDT 24 |
163501365 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3873516841 |
|
|
Jun 11 12:21:28 PM PDT 24 |
Jun 11 12:21:30 PM PDT 24 |
16361833 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3959592990 |
|
|
Jun 11 12:18:43 PM PDT 24 |
Jun 11 12:19:40 PM PDT 24 |
7053376402 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.940296945 |
|
|
Jun 11 12:17:39 PM PDT 24 |
Jun 11 12:17:40 PM PDT 24 |
45640929 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1533874419 |
|
|
Jun 11 12:23:36 PM PDT 24 |
Jun 11 12:23:41 PM PDT 24 |
17588279 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2964588400 |
|
|
Jun 11 12:22:31 PM PDT 24 |
Jun 11 12:22:36 PM PDT 24 |
23401278 ps |
| T108 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1739398347 |
|
|
Jun 11 12:23:20 PM PDT 24 |
Jun 11 12:23:25 PM PDT 24 |
185068327 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.486519804 |
|
|
Jun 11 12:23:47 PM PDT 24 |
Jun 11 12:23:55 PM PDT 24 |
99518571 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3527314009 |
|
|
Jun 11 12:23:37 PM PDT 24 |
Jun 11 12:23:45 PM PDT 24 |
2092830785 ps |
| T111 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.463596911 |
|
|
Jun 11 12:22:09 PM PDT 24 |
Jun 11 12:22:12 PM PDT 24 |
328568572 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2314239839 |
|
|
Jun 11 12:22:49 PM PDT 24 |
Jun 11 12:22:52 PM PDT 24 |
66911724 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3018723896 |
|
|
Jun 11 12:22:10 PM PDT 24 |
Jun 11 12:23:50 PM PDT 24 |
140944696943 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2709156283 |
|
|
Jun 11 12:21:52 PM PDT 24 |
Jun 11 12:21:55 PM PDT 24 |
290398707 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.501013263 |
|
|
Jun 11 12:22:55 PM PDT 24 |
Jun 11 12:23:00 PM PDT 24 |
164935890 ps |
| T953 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1203408351 |
|
|
Jun 11 12:22:45 PM PDT 24 |
Jun 11 12:22:51 PM PDT 24 |
372962850 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3187749907 |
|
|
Jun 11 12:18:03 PM PDT 24 |
Jun 11 12:18:08 PM PDT 24 |
1436411685 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.311546507 |
|
|
Jun 11 12:23:44 PM PDT 24 |
Jun 11 12:23:51 PM PDT 24 |
15805422 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.71860803 |
|
|
Jun 11 12:22:53 PM PDT 24 |
Jun 11 12:22:59 PM PDT 24 |
1425063137 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3390200481 |
|
|
Jun 11 12:22:49 PM PDT 24 |
Jun 11 12:22:55 PM PDT 24 |
1261971591 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3620957043 |
|
|
Jun 11 12:22:55 PM PDT 24 |
Jun 11 12:23:03 PM PDT 24 |
354632234 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.555313788 |
|
|
Jun 11 12:22:42 PM PDT 24 |
Jun 11 12:23:10 PM PDT 24 |
3771737564 ps |
| T115 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2502390347 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:36 PM PDT 24 |
285228569 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2452531844 |
|
|
Jun 11 12:22:55 PM PDT 24 |
Jun 11 12:22:58 PM PDT 24 |
13358486 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2128865350 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:34 PM PDT 24 |
13004735 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3538185443 |
|
|
Jun 11 12:22:56 PM PDT 24 |
Jun 11 12:23:26 PM PDT 24 |
3905898219 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2535587383 |
|
|
Jun 11 12:22:41 PM PDT 24 |
Jun 11 12:22:44 PM PDT 24 |
19004163 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3268117457 |
|
|
Jun 11 12:18:12 PM PDT 24 |
Jun 11 12:18:14 PM PDT 24 |
17329372 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2540791375 |
|
|
Jun 11 12:18:37 PM PDT 24 |
Jun 11 12:18:38 PM PDT 24 |
13785906 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.7103277 |
|
|
Jun 11 12:22:53 PM PDT 24 |
Jun 11 12:22:56 PM PDT 24 |
18803359 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4165213828 |
|
|
Jun 11 12:18:11 PM PDT 24 |
Jun 11 12:18:13 PM PDT 24 |
21764232 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3464551621 |
|
|
Jun 11 12:22:41 PM PDT 24 |
Jun 11 12:22:44 PM PDT 24 |
16949892 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2727198379 |
|
|
Jun 11 12:19:14 PM PDT 24 |
Jun 11 12:19:18 PM PDT 24 |
44256724 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1822619252 |
|
|
Jun 11 12:22:41 PM PDT 24 |
Jun 11 12:22:44 PM PDT 24 |
46750911 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3261447388 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:35 PM PDT 24 |
250452676 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.560233722 |
|
|
Jun 11 12:18:40 PM PDT 24 |
Jun 11 12:18:42 PM PDT 24 |
89380508 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.591957024 |
|
|
Jun 11 12:22:31 PM PDT 24 |
Jun 11 12:22:39 PM PDT 24 |
1430940658 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2155444903 |
|
|
Jun 11 12:23:26 PM PDT 24 |
Jun 11 12:23:34 PM PDT 24 |
347034816 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1102664007 |
|
|
Jun 11 12:20:41 PM PDT 24 |
Jun 11 12:21:10 PM PDT 24 |
15338558938 ps |
| T972 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3745552914 |
|
|
Jun 11 12:22:51 PM PDT 24 |
Jun 11 12:22:56 PM PDT 24 |
352674231 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3491241918 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:37 PM PDT 24 |
59946202 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.540021876 |
|
|
Jun 11 12:22:45 PM PDT 24 |
Jun 11 12:22:51 PM PDT 24 |
211564785 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.514900297 |
|
|
Jun 11 12:17:23 PM PDT 24 |
Jun 11 12:17:26 PM PDT 24 |
263630046 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3999671982 |
|
|
Jun 11 12:19:50 PM PDT 24 |
Jun 11 12:19:56 PM PDT 24 |
1615041143 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2120945544 |
|
|
Jun 11 12:18:29 PM PDT 24 |
Jun 11 12:18:33 PM PDT 24 |
1398693823 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1271351805 |
|
|
Jun 11 12:22:53 PM PDT 24 |
Jun 11 12:22:56 PM PDT 24 |
141836242 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2923395508 |
|
|
Jun 11 12:18:40 PM PDT 24 |
Jun 11 12:18:43 PM PDT 24 |
32997062 ps |
| T979 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.774265301 |
|
|
Jun 11 12:23:24 PM PDT 24 |
Jun 11 12:23:28 PM PDT 24 |
155471787 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1966204610 |
|
|
Jun 11 12:23:43 PM PDT 24 |
Jun 11 12:23:48 PM PDT 24 |
17474929 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2302452886 |
|
|
Jun 11 12:22:45 PM PDT 24 |
Jun 11 12:22:49 PM PDT 24 |
30560229 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1901317713 |
|
|
Jun 11 12:17:57 PM PDT 24 |
Jun 11 12:18:01 PM PDT 24 |
1432390035 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3929991469 |
|
|
Jun 11 12:20:41 PM PDT 24 |
Jun 11 12:20:44 PM PDT 24 |
127296123 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2479922010 |
|
|
Jun 11 12:18:43 PM PDT 24 |
Jun 11 12:18:48 PM PDT 24 |
746134071 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.65678852 |
|
|
Jun 11 12:22:27 PM PDT 24 |
Jun 11 12:22:31 PM PDT 24 |
243617338 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3603090416 |
|
|
Jun 11 12:22:47 PM PDT 24 |
Jun 11 12:22:50 PM PDT 24 |
19431093 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.193621532 |
|
|
Jun 11 12:22:55 PM PDT 24 |
Jun 11 12:22:59 PM PDT 24 |
107425838 ps |
| T81 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3884641714 |
|
|
Jun 11 12:23:36 PM PDT 24 |
Jun 11 12:24:10 PM PDT 24 |
7713526762 ps |
| T987 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1086759321 |
|
|
Jun 11 12:18:51 PM PDT 24 |
Jun 11 12:18:52 PM PDT 24 |
22162418 ps |
| T114 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4155770321 |
|
|
Jun 11 12:23:44 PM PDT 24 |
Jun 11 12:23:51 PM PDT 24 |
160659467 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4144486162 |
|
|
Jun 11 12:22:49 PM PDT 24 |
Jun 11 12:22:54 PM PDT 24 |
119392499 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3867336403 |
|
|
Jun 11 12:22:27 PM PDT 24 |
Jun 11 12:22:30 PM PDT 24 |
29417278 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2807574684 |
|
|
Jun 11 12:22:42 PM PDT 24 |
Jun 11 12:22:45 PM PDT 24 |
39530397 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2212726816 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:35 PM PDT 24 |
174982676 ps |
| T991 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.722641101 |
|
|
Jun 11 12:22:59 PM PDT 24 |
Jun 11 12:23:04 PM PDT 24 |
103747577 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3827213499 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:32 PM PDT 24 |
45345048 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2306746869 |
|
|
Jun 11 12:22:24 PM PDT 24 |
Jun 11 12:22:26 PM PDT 24 |
37825865 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4176891110 |
|
|
Jun 11 12:23:43 PM PDT 24 |
Jun 11 12:23:50 PM PDT 24 |
238994388 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3441150202 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:36 PM PDT 24 |
102007424 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1767440475 |
|
|
Jun 11 12:22:27 PM PDT 24 |
Jun 11 12:22:56 PM PDT 24 |
7414074651 ps |
| T82 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1703170745 |
|
|
Jun 11 12:19:52 PM PDT 24 |
Jun 11 12:20:49 PM PDT 24 |
7082902819 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.312994792 |
|
|
Jun 11 12:22:57 PM PDT 24 |
Jun 11 12:23:01 PM PDT 24 |
51963674 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3939381948 |
|
|
Jun 11 12:20:26 PM PDT 24 |
Jun 11 12:20:52 PM PDT 24 |
3816353449 ps |
| T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4127758794 |
|
|
Jun 11 12:19:52 PM PDT 24 |
Jun 11 12:19:55 PM PDT 24 |
19094586 ps |
| T999 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1978020646 |
|
|
Jun 11 12:22:48 PM PDT 24 |
Jun 11 12:22:51 PM PDT 24 |
20124692 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2577705764 |
|
|
Jun 11 12:22:29 PM PDT 24 |
Jun 11 12:22:35 PM PDT 24 |
80744704 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3763306995 |
|
|
Jun 11 12:22:47 PM PDT 24 |
Jun 11 12:22:52 PM PDT 24 |
144491044 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4228066955 |
|
|
Jun 11 12:22:30 PM PDT 24 |
Jun 11 12:22:34 PM PDT 24 |
28321263 ps |