Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	321540058	1			T1	393212		T2	501740		T4	9606
instr_valid_dis	281467278	1			T1	393212		T2	501740		T4	9606
instr_en	26161141	1			T23	195384		T18	475356		T28	364328

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14754359	1			T23	1154		T18	736310		T72	51416
sram_ifetch_valid_disable	279678741	1			T1	393212		T2	501740		T4	9606
sram_ifetch_enable	27106958	1			T23	109338		T24	32608		T18	467760

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	321540058	1			T1	393212		T2	501740		T4	9606
hw_debug_en_valid_off	280872543	1			T1	393212		T2	501740		T4	9606
hw_debug_en_on	26087737	1			T23	68828		T24	14354		T18	826896

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	279678741	1			T1	393212		T2	501740		T4	9606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	262487988	1			T1	393212		T2	501740		T4	9606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10720291	1			T23	84892		T18	119398		T28	169654
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7425644	1			T23	1154		T18	62572		T28	47566
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4512754	1			T18	47784		T64	54824		T148	45568
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1911052	1			T23	1154		T18	14788		T28	47566
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4735877	1			T18	620194		T28	57104		T62	60560
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2263256	1			T18	479944		T148	5710		T152	36954
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1725542	1			T18	118844		T28	57104		T62	60560
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11580636	1			T23	40178		T18	67278		T28	109326
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4502570	1			T18	15676		T148	16248		T19	89748
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4018608	1			T23	40178		T18	48812		T28	109326

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10688938	1			T23	109338		T18	194434		T28	27644
lc_exec_en	9771224	1			T23	28650		T24	14354		T18	139424
valid_exec_dis	271175465	1			T1	393212		T2	501740		T4	9606
invalid_exec_dis	41861317	1			T23	110492		T24	32608		T18	120407