Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv


Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
escalated_cp 2 0 2 100.00 100 1 1 2
key_seed_valid_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_seed_valid_cross 4 0 4 100.00 100 1 1 0


Summary for Variable escalated_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for escalated_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8179 1 T2 6 T4 24 T8 10
auto[1] 953 1 T4 15 T6 17 T7 12


Summary for Variable key_seed_valid_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_seed_valid_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4645 1 T4 18 T8 6 T5 1
auto[1] 4487 1 T2 6 T4 21 T8 4


Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key_seed_valid_cross

Bins
key_seed_valid_cpescalated_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 4166 1 T4 10 T8 6 T5 1
auto[0] auto[1] 479 1 T4 8 T6 8 T7 4
auto[1] auto[0] 4013 1 T2 6 T4 14 T8 4
auto[1] auto[1] 474 1 T4 7 T6 9 T7 8

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