Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	130321503	1			T1	196606		T2	228290		T4	319
triple_byte_access	2763232	1			T2	4528		T4	13		T5	3602
halfword_access	4240131	1			T2	6807		T4	8		T5	6530
byte_access	5935011	1			T2	9066		T4	11		T5	12734
zero_access	1804006	1			T2	2179		T4	2		T5	7501

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72297555

1

T1

65536

T2

125500

T4

182

auto[1]

72766328

1

T1

131070

T2

125370

T4

171

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	64782329	1			T1	65536		T2	114193		T4	166
auto[0]	triple_byte_access	1318373	1			T2	2265		T4	10		T5	661
auto[0]	halfword_access	2072282	1			T2	3415		T4	2		T5	2217
auto[0]	byte_access	3043016	1			T2	4533		T4	3		T5	6826
auto[0]	zero_access	1081555	1			T2	1094		T4	1		T5	5989
auto[1]	word_access	65539174	1			T1	131070		T2	114097		T4	153
auto[1]	triple_byte_access	1444859	1			T2	2263		T4	3		T5	2941
auto[1]	halfword_access	2167849	1			T2	3392		T4	6		T5	4313
auto[1]	byte_access	2891995	1			T2	4533		T4	8		T5	5908
auto[1]	zero_access	722451	1			T2	1085		T4	1		T5	1512