T794 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2157323195 |
|
|
Jun 13 01:56:27 PM PDT 24 |
Jun 13 02:02:06 PM PDT 24 |
47425806053 ps |
T795 |
/workspace/coverage/default/5.sram_ctrl_bijection.1981417867 |
|
|
Jun 13 01:56:09 PM PDT 24 |
Jun 13 02:17:34 PM PDT 24 |
70151745839 ps |
T796 |
/workspace/coverage/default/30.sram_ctrl_regwen.3572834922 |
|
|
Jun 13 02:19:23 PM PDT 24 |
Jun 13 02:35:23 PM PDT 24 |
16312882069 ps |
T797 |
/workspace/coverage/default/35.sram_ctrl_bijection.2611781150 |
|
|
Jun 13 02:18:45 PM PDT 24 |
Jun 13 02:38:06 PM PDT 24 |
48111640018 ps |
T798 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3811984095 |
|
|
Jun 13 02:03:23 PM PDT 24 |
Jun 13 02:12:25 PM PDT 24 |
8589763516 ps |
T799 |
/workspace/coverage/default/27.sram_ctrl_smoke.3434622487 |
|
|
Jun 13 02:31:48 PM PDT 24 |
Jun 13 02:32:12 PM PDT 24 |
3644038394 ps |
T800 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3512240508 |
|
|
Jun 13 01:55:54 PM PDT 24 |
Jun 13 01:58:06 PM PDT 24 |
4348630674 ps |
T801 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.4294760568 |
|
|
Jun 13 01:56:07 PM PDT 24 |
Jun 13 01:57:23 PM PDT 24 |
1461664078 ps |
T802 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1651046182 |
|
|
Jun 13 02:12:31 PM PDT 24 |
Jun 13 02:33:10 PM PDT 24 |
26691037593 ps |
T803 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3454434819 |
|
|
Jun 13 02:00:43 PM PDT 24 |
Jun 13 02:02:44 PM PDT 24 |
6352760800 ps |
T804 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2167264587 |
|
|
Jun 13 01:56:39 PM PDT 24 |
Jun 13 02:01:09 PM PDT 24 |
8221695944 ps |
T805 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3539571460 |
|
|
Jun 13 01:58:50 PM PDT 24 |
Jun 13 02:00:37 PM PDT 24 |
1542835722 ps |
T806 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.720405651 |
|
|
Jun 13 01:56:41 PM PDT 24 |
Jun 13 02:11:43 PM PDT 24 |
9479021152 ps |
T807 |
/workspace/coverage/default/43.sram_ctrl_partial_access.3090117772 |
|
|
Jun 13 02:02:13 PM PDT 24 |
Jun 13 02:03:19 PM PDT 24 |
1177389391 ps |
T808 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2241918812 |
|
|
Jun 13 02:19:37 PM PDT 24 |
Jun 13 02:25:43 PM PDT 24 |
54494754555 ps |
T809 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3490597286 |
|
|
Jun 13 01:56:21 PM PDT 24 |
Jun 13 01:57:50 PM PDT 24 |
2805913954 ps |
T810 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2600645876 |
|
|
Jun 13 01:56:03 PM PDT 24 |
Jun 13 01:58:59 PM PDT 24 |
10676145691 ps |
T811 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2471052103 |
|
|
Jun 13 02:19:08 PM PDT 24 |
Jun 13 02:23:06 PM PDT 24 |
52170874925 ps |
T812 |
/workspace/coverage/default/17.sram_ctrl_alert_test.911678536 |
|
|
Jun 13 01:57:17 PM PDT 24 |
Jun 13 01:57:20 PM PDT 24 |
24913380 ps |
T813 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.625803245 |
|
|
Jun 13 01:59:32 PM PDT 24 |
Jun 13 02:09:22 PM PDT 24 |
15964173927 ps |
T814 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3605309763 |
|
|
Jun 13 01:56:04 PM PDT 24 |
Jun 13 01:56:32 PM PDT 24 |
748034154 ps |
T815 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3235126308 |
|
|
Jun 13 01:58:51 PM PDT 24 |
Jun 13 02:02:44 PM PDT 24 |
9760178830 ps |
T816 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1698105149 |
|
|
Jun 13 01:55:56 PM PDT 24 |
Jun 13 02:00:37 PM PDT 24 |
6481769653 ps |
T817 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.925076565 |
|
|
Jun 13 01:59:36 PM PDT 24 |
Jun 13 02:00:08 PM PDT 24 |
8562746803 ps |
T818 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3707680489 |
|
|
Jun 13 02:00:13 PM PDT 24 |
Jun 13 02:01:02 PM PDT 24 |
1095089337 ps |
T819 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3095499243 |
|
|
Jun 13 01:58:20 PM PDT 24 |
Jun 13 02:08:14 PM PDT 24 |
18846788500 ps |
T820 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1283759451 |
|
|
Jun 13 02:02:15 PM PDT 24 |
Jun 13 02:05:05 PM PDT 24 |
10898540273 ps |
T821 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.4071974717 |
|
|
Jun 13 01:57:18 PM PDT 24 |
Jun 13 02:12:38 PM PDT 24 |
27179000124 ps |
T822 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.698496960 |
|
|
Jun 13 01:56:09 PM PDT 24 |
Jun 13 01:57:57 PM PDT 24 |
2902922869 ps |
T823 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3979501304 |
|
|
Jun 13 02:00:42 PM PDT 24 |
Jun 13 02:07:32 PM PDT 24 |
26313158264 ps |
T824 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3979000633 |
|
|
Jun 13 01:56:01 PM PDT 24 |
Jun 13 01:56:42 PM PDT 24 |
649349928 ps |
T825 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1611439120 |
|
|
Jun 13 02:03:27 PM PDT 24 |
Jun 13 02:03:46 PM PDT 24 |
6323760501 ps |
T826 |
/workspace/coverage/default/40.sram_ctrl_regwen.1777104321 |
|
|
Jun 13 02:01:40 PM PDT 24 |
Jun 13 02:21:47 PM PDT 24 |
59157510478 ps |
T827 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1265781593 |
|
|
Jun 13 01:56:29 PM PDT 24 |
Jun 13 01:56:40 PM PDT 24 |
679775203 ps |
T828 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1302149269 |
|
|
Jun 13 02:02:39 PM PDT 24 |
Jun 13 02:09:56 PM PDT 24 |
43084423063 ps |
T829 |
/workspace/coverage/default/41.sram_ctrl_executable.223938099 |
|
|
Jun 13 02:02:01 PM PDT 24 |
Jun 13 02:08:11 PM PDT 24 |
4343100187 ps |
T830 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.150735286 |
|
|
Jun 13 02:00:20 PM PDT 24 |
Jun 13 02:01:46 PM PDT 24 |
1540114023 ps |
T831 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3312872059 |
|
|
Jun 13 01:57:16 PM PDT 24 |
Jun 13 02:26:35 PM PDT 24 |
6971048324 ps |
T832 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.673412381 |
|
|
Jun 13 02:10:02 PM PDT 24 |
Jun 13 02:39:57 PM PDT 24 |
21296466942 ps |
T833 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3091402801 |
|
|
Jun 13 01:59:12 PM PDT 24 |
Jun 13 01:59:26 PM PDT 24 |
278603046 ps |
T834 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1833057899 |
|
|
Jun 13 02:00:37 PM PDT 24 |
Jun 13 02:03:32 PM PDT 24 |
13449654221 ps |
T835 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1450762617 |
|
|
Jun 13 01:56:31 PM PDT 24 |
Jun 13 01:57:42 PM PDT 24 |
26157923709 ps |
T836 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.953287652 |
|
|
Jun 13 02:00:55 PM PDT 24 |
Jun 13 02:06:59 PM PDT 24 |
55613555501 ps |
T837 |
/workspace/coverage/default/30.sram_ctrl_bijection.3924535361 |
|
|
Jun 13 01:59:39 PM PDT 24 |
Jun 13 02:14:07 PM PDT 24 |
12266193276 ps |
T838 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.976998428 |
|
|
Jun 13 01:56:02 PM PDT 24 |
Jun 13 02:05:13 PM PDT 24 |
42273116332 ps |
T839 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.27557343 |
|
|
Jun 13 01:58:11 PM PDT 24 |
Jun 13 02:01:27 PM PDT 24 |
22541587574 ps |
T840 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2805248311 |
|
|
Jun 13 02:03:14 PM PDT 24 |
Jun 13 02:08:47 PM PDT 24 |
7567473162 ps |
T841 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1490667410 |
|
|
Jun 13 01:56:19 PM PDT 24 |
Jun 13 02:06:28 PM PDT 24 |
4933296723 ps |
T842 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1791566737 |
|
|
Jun 13 02:02:49 PM PDT 24 |
Jun 13 02:05:04 PM PDT 24 |
3034290200 ps |
T843 |
/workspace/coverage/default/13.sram_ctrl_stress_all.4157988801 |
|
|
Jun 13 01:56:39 PM PDT 24 |
Jun 13 03:32:05 PM PDT 24 |
933036064461 ps |
T844 |
/workspace/coverage/default/33.sram_ctrl_stress_all.4019486573 |
|
|
Jun 13 02:00:10 PM PDT 24 |
Jun 13 02:56:01 PM PDT 24 |
11901705182 ps |
T845 |
/workspace/coverage/default/16.sram_ctrl_bijection.2614687801 |
|
|
Jun 13 01:56:58 PM PDT 24 |
Jun 13 02:28:11 PM PDT 24 |
166074944723 ps |
T846 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.337898427 |
|
|
Jun 13 01:59:42 PM PDT 24 |
Jun 13 02:09:45 PM PDT 24 |
93158844858 ps |
T847 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2972052917 |
|
|
Jun 13 01:56:01 PM PDT 24 |
Jun 13 02:05:02 PM PDT 24 |
95803143496 ps |
T848 |
/workspace/coverage/default/38.sram_ctrl_regwen.2514749061 |
|
|
Jun 13 02:01:19 PM PDT 24 |
Jun 13 02:20:53 PM PDT 24 |
79987571822 ps |
T849 |
/workspace/coverage/default/22.sram_ctrl_bijection.3300228041 |
|
|
Jun 13 01:58:04 PM PDT 24 |
Jun 13 02:12:05 PM PDT 24 |
12523997231 ps |
T850 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3081945613 |
|
|
Jun 13 02:02:47 PM PDT 24 |
Jun 13 02:03:06 PM PDT 24 |
2926657180 ps |
T851 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1178137189 |
|
|
Jun 13 01:56:15 PM PDT 24 |
Jun 13 01:56:17 PM PDT 24 |
13894530 ps |
T852 |
/workspace/coverage/default/7.sram_ctrl_bijection.1271094396 |
|
|
Jun 13 01:56:22 PM PDT 24 |
Jun 13 02:19:33 PM PDT 24 |
20859834259 ps |
T853 |
/workspace/coverage/default/27.sram_ctrl_bijection.2112913765 |
|
|
Jun 13 01:59:07 PM PDT 24 |
Jun 13 02:17:40 PM PDT 24 |
81971503459 ps |
T854 |
/workspace/coverage/default/45.sram_ctrl_executable.1743987258 |
|
|
Jun 13 02:02:47 PM PDT 24 |
Jun 13 02:24:12 PM PDT 24 |
145151486500 ps |
T855 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3914978561 |
|
|
Jun 13 01:56:18 PM PDT 24 |
Jun 13 01:56:20 PM PDT 24 |
28750968 ps |
T856 |
/workspace/coverage/default/32.sram_ctrl_smoke.3467084021 |
|
|
Jun 13 01:59:50 PM PDT 24 |
Jun 13 02:00:10 PM PDT 24 |
3581739840 ps |
T857 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1330706021 |
|
|
Jun 13 01:56:22 PM PDT 24 |
Jun 13 01:58:58 PM PDT 24 |
3127300199 ps |
T858 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2427879427 |
|
|
Jun 13 02:00:00 PM PDT 24 |
Jun 13 02:01:13 PM PDT 24 |
5650420744 ps |
T859 |
/workspace/coverage/default/47.sram_ctrl_bijection.1141150999 |
|
|
Jun 13 02:02:53 PM PDT 24 |
Jun 13 02:15:56 PM PDT 24 |
66210988752 ps |
T860 |
/workspace/coverage/default/42.sram_ctrl_bijection.2133511788 |
|
|
Jun 13 02:02:04 PM PDT 24 |
Jun 13 02:29:39 PM PDT 24 |
23816485063 ps |
T861 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2184709539 |
|
|
Jun 13 01:59:05 PM PDT 24 |
Jun 13 01:59:06 PM PDT 24 |
16267194 ps |
T862 |
/workspace/coverage/default/17.sram_ctrl_smoke.45942846 |
|
|
Jun 13 01:57:10 PM PDT 24 |
Jun 13 01:57:24 PM PDT 24 |
2660538731 ps |
T863 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2574131159 |
|
|
Jun 13 02:02:06 PM PDT 24 |
Jun 13 02:09:13 PM PDT 24 |
7953231365 ps |
T864 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.4005870964 |
|
|
Jun 13 01:56:04 PM PDT 24 |
Jun 13 01:56:25 PM PDT 24 |
4898290425 ps |
T865 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2557298035 |
|
|
Jun 13 01:56:28 PM PDT 24 |
Jun 13 02:16:32 PM PDT 24 |
20625777004 ps |
T866 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3886275428 |
|
|
Jun 13 01:59:07 PM PDT 24 |
Jun 13 02:08:05 PM PDT 24 |
89646617737 ps |
T867 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1801074802 |
|
|
Jun 13 02:02:12 PM PDT 24 |
Jun 13 02:02:39 PM PDT 24 |
775294409 ps |
T868 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1333452946 |
|
|
Jun 13 02:00:26 PM PDT 24 |
Jun 13 02:02:59 PM PDT 24 |
14324145130 ps |
T869 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.608658527 |
|
|
Jun 13 01:56:59 PM PDT 24 |
Jun 13 01:58:02 PM PDT 24 |
2061268462 ps |
T870 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1506957968 |
|
|
Jun 13 01:59:11 PM PDT 24 |
Jun 13 01:59:16 PM PDT 24 |
1977117181 ps |
T871 |
/workspace/coverage/default/30.sram_ctrl_executable.3161400160 |
|
|
Jun 13 02:20:57 PM PDT 24 |
Jun 13 02:24:07 PM PDT 24 |
18643348930 ps |
T872 |
/workspace/coverage/default/12.sram_ctrl_executable.2658111384 |
|
|
Jun 13 01:56:30 PM PDT 24 |
Jun 13 02:23:05 PM PDT 24 |
19118806143 ps |
T873 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1387560915 |
|
|
Jun 13 01:58:22 PM PDT 24 |
Jun 13 01:59:56 PM PDT 24 |
1703372102 ps |
T874 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3391650971 |
|
|
Jun 13 02:02:09 PM PDT 24 |
Jun 13 02:12:16 PM PDT 24 |
13030209658 ps |
T875 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1479097447 |
|
|
Jun 13 01:57:17 PM PDT 24 |
Jun 13 01:57:40 PM PDT 24 |
2284262133 ps |
T876 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2180844899 |
|
|
Jun 13 01:59:19 PM PDT 24 |
Jun 13 01:59:45 PM PDT 24 |
1140976593 ps |
T877 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2702157003 |
|
|
Jun 13 01:56:02 PM PDT 24 |
Jun 13 01:58:45 PM PDT 24 |
12205136698 ps |
T878 |
/workspace/coverage/default/23.sram_ctrl_bijection.4104744789 |
|
|
Jun 13 01:58:22 PM PDT 24 |
Jun 13 02:27:36 PM PDT 24 |
276325476423 ps |
T879 |
/workspace/coverage/default/46.sram_ctrl_bijection.2328414948 |
|
|
Jun 13 02:02:55 PM PDT 24 |
Jun 13 02:50:02 PM PDT 24 |
337757827852 ps |
T880 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1652902433 |
|
|
Jun 13 01:57:18 PM PDT 24 |
Jun 13 01:58:27 PM PDT 24 |
42990728788 ps |
T881 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3093237710 |
|
|
Jun 13 01:56:08 PM PDT 24 |
Jun 13 01:56:21 PM PDT 24 |
723263421 ps |
T882 |
/workspace/coverage/default/36.sram_ctrl_smoke.3301176798 |
|
|
Jun 13 02:00:42 PM PDT 24 |
Jun 13 02:02:50 PM PDT 24 |
4111437908 ps |
T883 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3982707980 |
|
|
Jun 13 01:57:57 PM PDT 24 |
Jun 13 01:58:03 PM PDT 24 |
361579752 ps |
T884 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.235690551 |
|
|
Jun 13 01:57:56 PM PDT 24 |
Jun 13 02:12:07 PM PDT 24 |
31311837508 ps |
T885 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2300964481 |
|
|
Jun 13 01:56:33 PM PDT 24 |
Jun 13 01:58:44 PM PDT 24 |
3080917718 ps |
T886 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.783878056 |
|
|
Jun 13 01:59:12 PM PDT 24 |
Jun 13 02:17:18 PM PDT 24 |
125407434141 ps |
T887 |
/workspace/coverage/default/35.sram_ctrl_regwen.2681840072 |
|
|
Jun 13 02:00:38 PM PDT 24 |
Jun 13 02:20:19 PM PDT 24 |
93587797293 ps |
T888 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.505319295 |
|
|
Jun 13 01:57:53 PM PDT 24 |
Jun 13 02:00:14 PM PDT 24 |
1582151410 ps |
T889 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3192143275 |
|
|
Jun 13 02:08:32 PM PDT 24 |
Jun 13 02:08:37 PM PDT 24 |
355847597 ps |
T890 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2793531642 |
|
|
Jun 13 02:02:07 PM PDT 24 |
Jun 13 02:04:20 PM PDT 24 |
1612965025 ps |
T891 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3337796174 |
|
|
Jun 13 01:59:44 PM PDT 24 |
Jun 13 02:01:27 PM PDT 24 |
766340740 ps |
T892 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2709191698 |
|
|
Jun 13 02:15:33 PM PDT 24 |
Jun 13 02:18:05 PM PDT 24 |
2555177364 ps |
T893 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.346995673 |
|
|
Jun 13 01:56:24 PM PDT 24 |
Jun 13 02:07:49 PM PDT 24 |
34641397675 ps |
T894 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3365640053 |
|
|
Jun 13 01:56:33 PM PDT 24 |
Jun 13 02:02:29 PM PDT 24 |
20662078340 ps |
T895 |
/workspace/coverage/default/31.sram_ctrl_smoke.3769945986 |
|
|
Jun 13 02:17:48 PM PDT 24 |
Jun 13 02:18:10 PM PDT 24 |
3162508501 ps |
T896 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3950250603 |
|
|
Jun 13 01:58:20 PM PDT 24 |
Jun 13 02:00:01 PM PDT 24 |
123901193120 ps |
T897 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2183229350 |
|
|
Jun 13 02:01:19 PM PDT 24 |
Jun 13 03:12:18 PM PDT 24 |
282801834252 ps |
T898 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3367033239 |
|
|
Jun 13 01:58:33 PM PDT 24 |
Jun 13 02:29:39 PM PDT 24 |
80910646688 ps |
T899 |
/workspace/coverage/default/45.sram_ctrl_bijection.225731960 |
|
|
Jun 13 02:02:36 PM PDT 24 |
Jun 13 02:25:06 PM PDT 24 |
149104065007 ps |
T900 |
/workspace/coverage/default/29.sram_ctrl_alert_test.68942710 |
|
|
Jun 13 01:59:31 PM PDT 24 |
Jun 13 01:59:33 PM PDT 24 |
33031116 ps |
T901 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.753930631 |
|
|
Jun 13 01:56:07 PM PDT 24 |
Jun 13 02:02:41 PM PDT 24 |
15887674257 ps |
T902 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1493011132 |
|
|
Jun 13 02:06:18 PM PDT 24 |
Jun 13 02:06:42 PM PDT 24 |
759566766 ps |
T903 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1707571693 |
|
|
Jun 13 01:55:55 PM PDT 24 |
Jun 13 02:01:26 PM PDT 24 |
55300048162 ps |
T904 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1413026059 |
|
|
Jun 13 01:56:22 PM PDT 24 |
Jun 13 01:56:28 PM PDT 24 |
1347459886 ps |
T905 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3997523573 |
|
|
Jun 13 01:57:11 PM PDT 24 |
Jun 13 01:58:04 PM PDT 24 |
1778449364 ps |
T906 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1410266541 |
|
|
Jun 13 01:56:22 PM PDT 24 |
Jun 13 01:57:16 PM PDT 24 |
1986968630 ps |
T907 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.613877682 |
|
|
Jun 13 01:57:46 PM PDT 24 |
Jun 13 01:58:20 PM PDT 24 |
2963603358 ps |
T908 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3211684227 |
|
|
Jun 13 01:57:10 PM PDT 24 |
Jun 13 01:57:28 PM PDT 24 |
12788359343 ps |
T909 |
/workspace/coverage/default/39.sram_ctrl_regwen.1804522149 |
|
|
Jun 13 02:01:26 PM PDT 24 |
Jun 13 02:14:22 PM PDT 24 |
14840712746 ps |
T910 |
/workspace/coverage/default/14.sram_ctrl_regwen.4097446306 |
|
|
Jun 13 01:56:46 PM PDT 24 |
Jun 13 02:15:02 PM PDT 24 |
13018454375 ps |
T911 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1720799314 |
|
|
Jun 13 02:04:50 PM PDT 24 |
Jun 13 02:05:31 PM PDT 24 |
26285288284 ps |
T912 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1980148653 |
|
|
Jun 13 01:56:02 PM PDT 24 |
Jun 13 02:01:38 PM PDT 24 |
9784087684 ps |
T913 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.111059873 |
|
|
Jun 13 01:56:33 PM PDT 24 |
Jun 13 01:57:51 PM PDT 24 |
961376052 ps |
T914 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3190926896 |
|
|
Jun 13 02:03:08 PM PDT 24 |
Jun 13 02:04:19 PM PDT 24 |
2338439261 ps |
T915 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3536239776 |
|
|
Jun 13 02:03:14 PM PDT 24 |
Jun 13 02:29:02 PM PDT 24 |
90769839061 ps |
T916 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3366045894 |
|
|
Jun 13 02:01:48 PM PDT 24 |
Jun 13 02:01:50 PM PDT 24 |
12052079 ps |
T917 |
/workspace/coverage/default/31.sram_ctrl_regwen.3892517237 |
|
|
Jun 13 02:14:45 PM PDT 24 |
Jun 13 02:31:40 PM PDT 24 |
10201649286 ps |
T918 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2927994106 |
|
|
Jun 13 01:56:33 PM PDT 24 |
Jun 13 02:20:08 PM PDT 24 |
32685105321 ps |
T919 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.798658852 |
|
|
Jun 13 01:56:04 PM PDT 24 |
Jun 13 02:20:38 PM PDT 24 |
78668637865 ps |
T920 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1374152274 |
|
|
Jun 13 02:01:14 PM PDT 24 |
Jun 13 02:02:13 PM PDT 24 |
44489658088 ps |
T921 |
/workspace/coverage/default/39.sram_ctrl_smoke.2554888811 |
|
|
Jun 13 02:01:20 PM PDT 24 |
Jun 13 02:03:14 PM PDT 24 |
10586433656 ps |
T922 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2982069284 |
|
|
Jun 13 02:01:37 PM PDT 24 |
Jun 13 02:07:14 PM PDT 24 |
57732576071 ps |
T923 |
/workspace/coverage/default/38.sram_ctrl_bijection.2566778928 |
|
|
Jun 13 02:01:14 PM PDT 24 |
Jun 13 02:16:01 PM PDT 24 |
50564679274 ps |
T924 |
/workspace/coverage/default/39.sram_ctrl_executable.439939842 |
|
|
Jun 13 02:01:20 PM PDT 24 |
Jun 13 02:01:39 PM PDT 24 |
2223386491 ps |
T925 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.106888610 |
|
|
Jun 13 01:58:04 PM PDT 24 |
Jun 13 02:28:40 PM PDT 24 |
50109084939 ps |
T926 |
/workspace/coverage/default/10.sram_ctrl_smoke.2800871232 |
|
|
Jun 13 01:56:31 PM PDT 24 |
Jun 13 01:59:01 PM PDT 24 |
1942026267 ps |
T927 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3777157356 |
|
|
Jun 13 01:59:19 PM PDT 24 |
Jun 13 03:39:34 PM PDT 24 |
224450087778 ps |
T928 |
/workspace/coverage/default/14.sram_ctrl_executable.2711949335 |
|
|
Jun 13 01:56:37 PM PDT 24 |
Jun 13 02:01:48 PM PDT 24 |
11663405430 ps |
T929 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1910229738 |
|
|
Jun 13 01:56:38 PM PDT 24 |
Jun 13 01:56:41 PM PDT 24 |
38744480 ps |
T930 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2926441365 |
|
|
Jun 13 01:57:53 PM PDT 24 |
Jun 13 02:01:04 PM PDT 24 |
3820948959 ps |
T931 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1354126301 |
|
|
Jun 13 01:59:42 PM PDT 24 |
Jun 13 02:00:26 PM PDT 24 |
7053330303 ps |
T932 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.588526356 |
|
|
Jun 13 01:57:05 PM PDT 24 |
Jun 13 01:57:22 PM PDT 24 |
1419235274 ps |
T933 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2332316826 |
|
|
Jun 13 01:58:32 PM PDT 24 |
Jun 13 01:58:37 PM PDT 24 |
697220532 ps |
T934 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2268611522 |
|
|
Jun 13 01:56:21 PM PDT 24 |
Jun 13 01:58:33 PM PDT 24 |
1778650110 ps |
T935 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2216694383 |
|
|
Jun 13 02:03:06 PM PDT 24 |
Jun 13 02:03:17 PM PDT 24 |
1301035582 ps |
T936 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1307461742 |
|
|
Jun 13 02:00:43 PM PDT 24 |
Jun 13 02:00:45 PM PDT 24 |
14769021 ps |
T937 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2794043350 |
|
|
Jun 13 01:56:07 PM PDT 24 |
Jun 13 01:56:13 PM PDT 24 |
1402864447 ps |
T938 |
/workspace/coverage/default/9.sram_ctrl_smoke.2758515255 |
|
|
Jun 13 01:56:22 PM PDT 24 |
Jun 13 01:57:02 PM PDT 24 |
2511933108 ps |
T939 |
/workspace/coverage/default/49.sram_ctrl_bijection.205300214 |
|
|
Jun 13 02:03:23 PM PDT 24 |
Jun 13 02:54:07 PM PDT 24 |
311418469458 ps |
T940 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3462810496 |
|
|
Jun 13 01:56:40 PM PDT 24 |
Jun 13 01:58:49 PM PDT 24 |
776378816 ps |
T33 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1313318081 |
|
|
Jun 13 01:56:04 PM PDT 24 |
Jun 13 01:56:09 PM PDT 24 |
694586073 ps |
T941 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3524708120 |
|
|
Jun 13 01:56:38 PM PDT 24 |
Jun 13 01:57:05 PM PDT 24 |
3413855656 ps |
T942 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1973294738 |
|
|
Jun 13 01:59:18 PM PDT 24 |
Jun 13 02:27:25 PM PDT 24 |
343234565024 ps |
T943 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2736313782 |
|
|
Jun 13 01:57:07 PM PDT 24 |
Jun 13 01:57:11 PM PDT 24 |
692797520 ps |
T73 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.999771390 |
|
|
Jun 13 12:45:32 PM PDT 24 |
Jun 13 12:45:33 PM PDT 24 |
80876843 ps |
T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.17278181 |
|
|
Jun 13 12:45:26 PM PDT 24 |
Jun 13 12:45:29 PM PDT 24 |
46877946 ps |
T74 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.185680234 |
|
|
Jun 13 12:45:11 PM PDT 24 |
Jun 13 12:45:12 PM PDT 24 |
50260979 ps |
T945 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1556774173 |
|
|
Jun 13 12:45:14 PM PDT 24 |
Jun 13 12:45:16 PM PDT 24 |
66385785 ps |
T69 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4017981570 |
|
|
Jun 13 12:45:03 PM PDT 24 |
Jun 13 12:45:06 PM PDT 24 |
613641439 ps |
T83 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2375948894 |
|
|
Jun 13 12:45:19 PM PDT 24 |
Jun 13 12:45:20 PM PDT 24 |
18830586 ps |
T946 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1461198693 |
|
|
Jun 13 12:45:14 PM PDT 24 |
Jun 13 12:45:19 PM PDT 24 |
158163885 ps |
T70 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2161789471 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:02 PM PDT 24 |
98104076 ps |
T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3652805583 |
|
|
Jun 13 12:45:26 PM PDT 24 |
Jun 13 12:45:29 PM PDT 24 |
844438818 ps |
T133 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3112382214 |
|
|
Jun 13 12:45:14 PM PDT 24 |
Jun 13 12:45:17 PM PDT 24 |
1771119760 ps |
T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2729936390 |
|
|
Jun 13 12:45:29 PM PDT 24 |
Jun 13 12:45:32 PM PDT 24 |
765273064 ps |
T109 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.803850890 |
|
|
Jun 13 12:45:02 PM PDT 24 |
Jun 13 12:45:03 PM PDT 24 |
90574782 ps |
T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3386764425 |
|
|
Jun 13 12:44:48 PM PDT 24 |
Jun 13 12:44:49 PM PDT 24 |
65294574 ps |
T85 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2239154353 |
|
|
Jun 13 12:45:09 PM PDT 24 |
Jun 13 12:46:01 PM PDT 24 |
14149544376 ps |
T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1868683010 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:51 PM PDT 24 |
14359467147 ps |
T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3932581128 |
|
|
Jun 13 12:44:58 PM PDT 24 |
Jun 13 12:45:04 PM PDT 24 |
295223536 ps |
T87 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1066577993 |
|
|
Jun 13 12:45:10 PM PDT 24 |
Jun 13 12:45:11 PM PDT 24 |
13353187 ps |
T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3305145285 |
|
|
Jun 13 12:45:01 PM PDT 24 |
Jun 13 12:45:07 PM PDT 24 |
347896968 ps |
T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1658164952 |
|
|
Jun 13 12:45:03 PM PDT 24 |
Jun 13 12:45:04 PM PDT 24 |
14211590 ps |
T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4095381589 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:01 PM PDT 24 |
29376249 ps |
T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.529788128 |
|
|
Jun 13 12:45:12 PM PDT 24 |
Jun 13 12:45:18 PM PDT 24 |
374153790 ps |
T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2867190745 |
|
|
Jun 13 12:44:55 PM PDT 24 |
Jun 13 12:44:56 PM PDT 24 |
12540961 ps |
T135 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2922717774 |
|
|
Jun 13 12:45:35 PM PDT 24 |
Jun 13 12:45:37 PM PDT 24 |
97767254 ps |
T88 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1077516893 |
|
|
Jun 13 12:45:08 PM PDT 24 |
Jun 13 12:45:59 PM PDT 24 |
13642599553 ps |
T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3974348281 |
|
|
Jun 13 12:45:28 PM PDT 24 |
Jun 13 12:45:29 PM PDT 24 |
15093175 ps |
T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.593286582 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:22 PM PDT 24 |
29302282 ps |
T136 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1022798146 |
|
|
Jun 13 12:45:26 PM PDT 24 |
Jun 13 12:45:30 PM PDT 24 |
555705844 ps |
T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1870577189 |
|
|
Jun 13 12:45:13 PM PDT 24 |
Jun 13 12:45:14 PM PDT 24 |
18390506 ps |
T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2271510492 |
|
|
Jun 13 12:45:29 PM PDT 24 |
Jun 13 12:46:17 PM PDT 24 |
7265961991 ps |
T143 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3484709144 |
|
|
Jun 13 12:45:12 PM PDT 24 |
Jun 13 12:45:14 PM PDT 24 |
594427022 ps |
T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3486619992 |
|
|
Jun 13 12:44:58 PM PDT 24 |
Jun 13 12:44:59 PM PDT 24 |
23682617 ps |
T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3689815022 |
|
|
Jun 13 12:44:57 PM PDT 24 |
Jun 13 12:44:58 PM PDT 24 |
42903129 ps |
T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.421512946 |
|
|
Jun 13 12:44:55 PM PDT 24 |
Jun 13 12:44:58 PM PDT 24 |
116709272 ps |
T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3908658007 |
|
|
Jun 13 12:45:11 PM PDT 24 |
Jun 13 12:45:39 PM PDT 24 |
3791882782 ps |
T93 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.849543157 |
|
|
Jun 13 12:45:26 PM PDT 24 |
Jun 13 12:46:19 PM PDT 24 |
7266391026 ps |
T958 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3516042332 |
|
|
Jun 13 12:45:36 PM PDT 24 |
Jun 13 12:45:41 PM PDT 24 |
1416181839 ps |
T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4006391767 |
|
|
Jun 13 12:44:49 PM PDT 24 |
Jun 13 12:44:50 PM PDT 24 |
17417212 ps |
T134 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3652868637 |
|
|
Jun 13 12:45:28 PM PDT 24 |
Jun 13 12:45:31 PM PDT 24 |
388817711 ps |
T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3868889474 |
|
|
Jun 13 12:44:56 PM PDT 24 |
Jun 13 12:44:57 PM PDT 24 |
25895476 ps |
T960 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.579536298 |
|
|
Jun 13 12:45:10 PM PDT 24 |
Jun 13 12:45:11 PM PDT 24 |
38776389 ps |
T102 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2068094342 |
|
|
Jun 13 12:45:27 PM PDT 24 |
Jun 13 12:45:28 PM PDT 24 |
59844993 ps |
T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3566093713 |
|
|
Jun 13 12:44:59 PM PDT 24 |
Jun 13 12:45:00 PM PDT 24 |
26255753 ps |
T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1930180903 |
|
|
Jun 13 12:44:57 PM PDT 24 |
Jun 13 12:45:50 PM PDT 24 |
15012044241 ps |
T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1089427330 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:03 PM PDT 24 |
84291357 ps |
T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1364066297 |
|
|
Jun 13 12:45:25 PM PDT 24 |
Jun 13 12:45:29 PM PDT 24 |
713783200 ps |
T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.786679326 |
|
|
Jun 13 12:45:12 PM PDT 24 |
Jun 13 12:45:13 PM PDT 24 |
29482262 ps |
T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.737325433 |
|
|
Jun 13 12:44:48 PM PDT 24 |
Jun 13 12:44:50 PM PDT 24 |
80121983 ps |
T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.344870635 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:23 PM PDT 24 |
366447826 ps |
T97 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1853844097 |
|
|
Jun 13 12:45:28 PM PDT 24 |
Jun 13 12:45:29 PM PDT 24 |
16242941 ps |
T98 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2477341223 |
|
|
Jun 13 12:45:24 PM PDT 24 |
Jun 13 12:45:49 PM PDT 24 |
3871097169 ps |
T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1142984361 |
|
|
Jun 13 12:45:36 PM PDT 24 |
Jun 13 12:45:38 PM PDT 24 |
23827657 ps |
T103 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2316450794 |
|
|
Jun 13 12:45:37 PM PDT 24 |
Jun 13 12:46:33 PM PDT 24 |
28191163170 ps |
T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1123727335 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:25 PM PDT 24 |
374814498 ps |
T968 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.93504367 |
|
|
Jun 13 12:45:03 PM PDT 24 |
Jun 13 12:45:07 PM PDT 24 |
1424837397 ps |
T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3311941536 |
|
|
Jun 13 12:44:55 PM PDT 24 |
Jun 13 12:44:56 PM PDT 24 |
15658247 ps |
T106 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2052237383 |
|
|
Jun 13 12:44:50 PM PDT 24 |
Jun 13 12:44:51 PM PDT 24 |
16037553 ps |
T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.993378439 |
|
|
Jun 13 12:45:12 PM PDT 24 |
Jun 13 12:45:16 PM PDT 24 |
350768096 ps |
T140 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2198392316 |
|
|
Jun 13 12:45:06 PM PDT 24 |
Jun 13 12:45:07 PM PDT 24 |
446465933 ps |
T970 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.995385759 |
|
|
Jun 13 12:45:31 PM PDT 24 |
Jun 13 12:45:33 PM PDT 24 |
49091550 ps |
T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.550533933 |
|
|
Jun 13 12:45:20 PM PDT 24 |
Jun 13 12:45:24 PM PDT 24 |
365933012 ps |
T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1662904634 |
|
|
Jun 13 12:45:37 PM PDT 24 |
Jun 13 12:45:38 PM PDT 24 |
11792603 ps |
T141 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1038885357 |
|
|
Jun 13 12:44:56 PM PDT 24 |
Jun 13 12:44:59 PM PDT 24 |
642600688 ps |
T107 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2253241297 |
|
|
Jun 13 12:45:31 PM PDT 24 |
Jun 13 12:46:25 PM PDT 24 |
14120467441 ps |
T144 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2980769952 |
|
|
Jun 13 12:44:55 PM PDT 24 |
Jun 13 12:44:58 PM PDT 24 |
220519296 ps |
T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2313930357 |
|
|
Jun 13 12:44:48 PM PDT 24 |
Jun 13 12:44:53 PM PDT 24 |
1294225647 ps |
T974 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3061313340 |
|
|
Jun 13 12:45:37 PM PDT 24 |
Jun 13 12:45:41 PM PDT 24 |
1302861878 ps |
T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2657024854 |
|
|
Jun 13 12:44:49 PM PDT 24 |
Jun 13 12:44:54 PM PDT 24 |
1437149035 ps |
T146 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3565359079 |
|
|
Jun 13 12:45:11 PM PDT 24 |
Jun 13 12:45:14 PM PDT 24 |
633582607 ps |
T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2980275781 |
|
|
Jun 13 12:44:50 PM PDT 24 |
Jun 13 12:44:51 PM PDT 24 |
21726023 ps |
T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1354753740 |
|
|
Jun 13 12:44:43 PM PDT 24 |
Jun 13 12:45:11 PM PDT 24 |
15540144044 ps |
T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1711268174 |
|
|
Jun 13 12:44:56 PM PDT 24 |
Jun 13 12:44:59 PM PDT 24 |
417320906 ps |
T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1889889330 |
|
|
Jun 13 12:45:23 PM PDT 24 |
Jun 13 12:45:26 PM PDT 24 |
446536100 ps |
T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1797552631 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:22 PM PDT 24 |
25884321 ps |
T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4187694028 |
|
|
Jun 13 12:44:59 PM PDT 24 |
Jun 13 12:45:00 PM PDT 24 |
25293898 ps |
T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1764230367 |
|
|
Jun 13 12:45:13 PM PDT 24 |
Jun 13 12:45:15 PM PDT 24 |
37939142 ps |
T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1089210871 |
|
|
Jun 13 12:45:26 PM PDT 24 |
Jun 13 12:45:30 PM PDT 24 |
351194763 ps |
T984 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1882358339 |
|
|
Jun 13 12:44:50 PM PDT 24 |
Jun 13 12:44:52 PM PDT 24 |
178424442 ps |
T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2968724699 |
|
|
Jun 13 12:45:33 PM PDT 24 |
Jun 13 12:45:34 PM PDT 24 |
21699268 ps |
T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1218300815 |
|
|
Jun 13 12:45:01 PM PDT 24 |
Jun 13 12:45:05 PM PDT 24 |
1796751766 ps |
T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3640398267 |
|
|
Jun 13 12:44:59 PM PDT 24 |
Jun 13 12:45:01 PM PDT 24 |
196113736 ps |
T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.772254558 |
|
|
Jun 13 12:45:09 PM PDT 24 |
Jun 13 12:45:10 PM PDT 24 |
13592125 ps |
T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.228379861 |
|
|
Jun 13 12:45:03 PM PDT 24 |
Jun 13 12:46:00 PM PDT 24 |
30637026626 ps |
T990 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2046345144 |
|
|
Jun 13 12:45:08 PM PDT 24 |
Jun 13 12:45:11 PM PDT 24 |
70903291 ps |
T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4025124117 |
|
|
Jun 13 12:44:55 PM PDT 24 |
Jun 13 12:44:58 PM PDT 24 |
123678565 ps |
T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4224833740 |
|
|
Jun 13 12:45:11 PM PDT 24 |
Jun 13 12:45:16 PM PDT 24 |
1463951464 ps |
T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1521278774 |
|
|
Jun 13 12:45:19 PM PDT 24 |
Jun 13 12:45:20 PM PDT 24 |
27267277 ps |
T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3453090079 |
|
|
Jun 13 12:44:48 PM PDT 24 |
Jun 13 12:44:51 PM PDT 24 |
25475509 ps |
T105 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1586409242 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:51 PM PDT 24 |
9742817016 ps |
T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.45462588 |
|
|
Jun 13 12:44:57 PM PDT 24 |
Jun 13 12:44:58 PM PDT 24 |
20905425 ps |
T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2487156438 |
|
|
Jun 13 12:44:56 PM PDT 24 |
Jun 13 12:44:57 PM PDT 24 |
59802121 ps |
T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2113379463 |
|
|
Jun 13 12:45:27 PM PDT 24 |
Jun 13 12:45:28 PM PDT 24 |
42190290 ps |
T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3486965665 |
|
|
Jun 13 12:45:25 PM PDT 24 |
Jun 13 12:45:31 PM PDT 24 |
1554697071 ps |
T999 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2384699205 |
|
|
Jun 13 12:45:09 PM PDT 24 |
Jun 13 12:45:14 PM PDT 24 |
141712975 ps |
T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.592177222 |
|
|
Jun 13 12:45:21 PM PDT 24 |
Jun 13 12:45:22 PM PDT 24 |
21894262 ps |
T137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2653969227 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:03 PM PDT 24 |
793535182 ps |
T142 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3737521438 |
|
|
Jun 13 12:45:19 PM PDT 24 |
Jun 13 12:45:22 PM PDT 24 |
342480342 ps |
T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2505803393 |
|
|
Jun 13 12:45:00 PM PDT 24 |
Jun 13 12:45:01 PM PDT 24 |
15459865 ps |
T1002 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4143798033 |
|
|
Jun 13 12:45:35 PM PDT 24 |
Jun 13 12:45:36 PM PDT 24 |
13376927 ps |
T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3387261198 |
|
|
Jun 13 12:45:12 PM PDT 24 |
Jun 13 12:45:40 PM PDT 24 |
3730183858 ps |