Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	333352278	1			T1	16590		T2	350944		T3	62998
instr_valid_dis	295833204	1			T1	16590		T2	350944		T3	62998
instr_en	28652854	1			T28	144758		T66	278526		T127	86196

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13871226	1			T10	29682		T12	61034		T28	23490
sram_ifetch_valid_disable	296846712	1			T1	16590		T2	350944		T3	62998
sram_ifetch_enable	22634340	1			T10	105962		T12	193554		T28	94324

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	333352278	1			T1	16590		T2	350944		T3	62998
hw_debug_en_valid_off	287568700	1			T1	16590		T2	350944		T3	62998
hw_debug_en_on	35247778	1			T10	57692		T12	115418		T28	63388

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	296846712	1			T1	16590		T2	350944		T3	62998
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	281801148	1			T1	16590		T2	350944		T3	62998
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11204548	1			T28	83298		T66	102884		T127	38310
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4213820	1			T10	29682		T12	20000		T28	9842
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1938250	1			T10	29682		T28	9842		T24	52154
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1536910	1			T66	65280		T127	37408		T131	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7478252	1			T12	41034		T66	63806		T127	69442
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1671538	1			T127	69442		T20	58336		T24	6662
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	5075692	1			T66	63806		T4	79558		T22	46366
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	18971772	1			T10	24814		T12	30542		T28	49408
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	11460098	1			T10	24814		T28	36368		T127	38196
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5924922	1			T28	13040		T66	18302		T127	15786

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9845012	1			T28	61460		T66	38946		T127	10478
lc_exec_en	8797754	1			T10	32878		T12	43842		T28	13980
valid_exec_dis	283742306	1			T1	16590		T2	350944		T3	62998
invalid_exec_dis	36505566	1			T10	135644		T12	254588		T28	117814