Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	137288182	1			T1	1507		T2	32067		T3	1539
triple_byte_access	2806579	1			T1	1353		T2	28630		T3	3474
halfword_access	4307961	1			T1	2026		T2	42815		T3	6629
byte_access	6029816	1			T1	2752		T2	57524		T3	12420
zero_access	1831558	1			T1	657		T2	14436		T3	7437

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75937187

1

T1

4157

T2

87758

T3

15715

auto[1]

76326909

1

T1

4138

T2

87714

T3

15784

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68303920	1			T1	765		T2	15934		T3	125
auto[0]	triple_byte_access	1338510	1			T1	688		T2	14411		T3	669
auto[0]	halfword_access	2105135	1			T1	994		T2	21504		T3	2272
auto[0]	byte_access	3092226	1			T1	1392		T2	28618		T3	6683
auto[0]	zero_access	1097396	1			T1	318		T2	7291		T3	5966
auto[1]	word_access	68984262	1			T1	742		T2	16133		T3	1414
auto[1]	triple_byte_access	1468069	1			T1	665		T2	14219		T3	2805
auto[1]	halfword_access	2202826	1			T1	1032		T2	21311		T3	4357
auto[1]	byte_access	2937590	1			T1	1360		T2	28906		T3	5737
auto[1]	zero_access	734162	1			T1	339		T2	7145		T3	1471