Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	368572906	1			T1	13530		T2	438620		T3	60758
instr_valid_dis	319732920	1			T1	13530		T2	438620		T3	60758
instr_en	37320843	1			T12	224746		T7	300986		T24	264368

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	16020058	1			T12	123270		T7	197868		T24	84100
sram_ifetch_valid_disable	324788734	1			T1	13530		T2	438620		T3	60758
sram_ifetch_enable	27764114	1			T12	30110		T7	169992		T24	51680

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	368572906	1			T1	13530		T2	438620		T3	60758
hw_debug_en_valid_off	323631438	1			T1	13530		T2	438620		T3	60758
hw_debug_en_on	31878560	1			T12	86314		T7	110290		T24	128012

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	324788734	1			T1	13530		T2	438620		T3	60758
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	305849080	1			T1	13530		T2	438620		T3	60758
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13014317	1			T12	93248		T7	72264		T24	128588
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3775462	1			T12	33518		T7	40908		T19	59328
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1674160	1			T7	5570		T19	59328		T20	62488
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1372616	1			T12	33518		T7	35338		T128	127094
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	8581168	1			T12	55208		T7	40386		T24	56270
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2282988	1			T12	11772		T7	23920		T19	60418
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	5524334	1			T12	43436		T24	56270		T44	95192
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14921900	1			T12	31106		T7	69400		T24	61862
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3357000	1			T7	55212		T19	107906		T20	20736
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7361140	1			T12	31106		T7	14188		T24	61862

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15543372	1			T12	20000		T7	118610		T24	51680
lc_exec_en	8375492	1			T7	504		T24	9880		T19	146192
valid_exec_dis	314229188	1			T1	13530		T2	438620		T3	60758
invalid_exec_dis	43784172	1			T12	153380		T7	367860		T24	135780