Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153700650	1			T1	35		T2	199304		T3	1476
triple_byte_access	2858254	1			T1	2		T2	3924		T3	3483
halfword_access	4388695	1			T1	1		T2	6045		T3	6465
byte_access	6139752	1			T1	2		T2	8054		T3	12007
zero_access	1856979	1			T1	1		T2	1983		T3	6948

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84329704

1

T1

12

T2

109382

T3

14919

auto[1]

84614626

1

T1

29

T2

109928

T3

15460

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76558323	1			T1	9		T2	99457		T3	118
auto[0]	triple_byte_access	1365900	1			T2	1970		T3	636		T4	22018
auto[0]	halfword_access	2147236	1			T1	1		T2	2984		T3	2229
auto[0]	byte_access	3148416	1			T1	1		T2	3982		T3	6412
auto[0]	zero_access	1109829	1			T1	1		T2	989		T3	5524
auto[1]	word_access	77142327	1			T1	26		T2	99847		T3	1358
auto[1]	triple_byte_access	1492354	1			T1	2		T2	1954		T3	2847
auto[1]	halfword_access	2241459	1			T2	3061		T3	4236		T4	33087
auto[1]	byte_access	2991336	1			T1	1		T2	4072		T3	5595
auto[1]	zero_access	747150	1			T2	994		T3	1424		T4	11080