Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	364971110	1			T1	393212		T2	15910		T3	320648
instr_valid_dis	326793768	1			T1	393212		T2	15910		T3	162410
instr_en	31306016	1			T3	88514		T8	277030		T10	376138

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11279768	1			T3	27374		T8	96526		T10	17902
sram_ifetch_valid_disable	331960296	1			T1	393212		T2	15910		T3	177778
sram_ifetch_enable	21731046	1			T3	115496		T8	76222		T10	239952

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	364971110	1			T1	393212		T2	15910		T3	320648
hw_debug_en_valid_off	323017180	1			T1	393212		T2	15910		T3	172154
hw_debug_en_on	26800742	1			T3	148494		T8	180504		T10	265050

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	331960296	1			T1	393212		T2	15910		T3	177778
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	313656814	1			T1	393212		T2	15910		T3	128054
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15573344	1			T8	104282		T10	118284		T21	107140
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4049974	1			T3	20000		T8	65716		T21	33718
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1787592	1			T81	86220		T32	13112		T152	24252
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1641416	1			T3	20000		T8	65716		T21	33718
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4361828	1			T3	7374		T10	17902		T21	28622
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2082238	1			T81	27956		T152	11838		T153	16828
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1836554	1			T3	7374		T10	17902		T21	28622
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13064834	1			T3	93814		T8	104282		T10	49988
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6237282	1			T3	93814		T10	1212		T21	31112
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5989530	1			T8	104282		T10	48776		T21	107140

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11149414	1			T3	61140		T8	76222		T10	239952
lc_exec_en	9374080	1			T3	47306		T8	76222		T10	197160
valid_exec_dis	318475312	1			T1	393212		T2	15910		T3	118320
invalid_exec_dis	33010814	1			T3	142870		T8	172748		T10	257854