Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153781148	1			T1	196606		T2	7955		T3	73026
triple_byte_access	2838679	1			T3	1477		T4	1924		T5	24278
halfword_access	4344178	1			T3	2103		T4	2768		T5	36077
byte_access	6084129	1			T3	2903		T4	3803		T5	47820
zero_access	1838822	1			T3	725		T4	959		T5	12310

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84340736

1

T1

65536

T2

3884

T3

48193

auto[1]

84546220

1

T1

131070

T2

4071

T3

32041

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76648048	1			T1	65536		T2	3884		T3	43807
auto[0]	triple_byte_access	1355728	1			T3	897		T4	960		T5	12125
auto[0]	halfword_access	2122336	1			T3	1315		T4	1396		T5	18009
auto[0]	byte_access	3116404	1			T3	1737		T4	1908		T5	24048
auto[0]	zero_access	1098220	1			T3	437		T4	479		T5	6212
auto[1]	word_access	77133100	1			T1	131070		T2	4071		T3	29219
auto[1]	triple_byte_access	1482951	1			T3	580		T4	964		T5	12153
auto[1]	halfword_access	2221842	1			T3	788		T4	1372		T5	18068
auto[1]	byte_access	2967725	1			T3	1166		T4	1895		T5	23772
auto[1]	zero_access	740602	1			T3	288		T4	480		T5	6098