Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1037
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T790 /workspace/coverage/default/6.sram_ctrl_alert_test.306866717 Jun 25 04:48:45 PM PDT 24 Jun 25 04:49:00 PM PDT 24 63271634 ps
T791 /workspace/coverage/default/39.sram_ctrl_multiple_keys.921982235 Jun 25 04:50:32 PM PDT 24 Jun 25 05:28:50 PM PDT 24 37286362980 ps
T792 /workspace/coverage/default/26.sram_ctrl_smoke.56356165 Jun 25 04:49:42 PM PDT 24 Jun 25 04:50:26 PM PDT 24 1039198113 ps
T793 /workspace/coverage/default/16.sram_ctrl_executable.1824764185 Jun 25 04:49:14 PM PDT 24 Jun 25 04:57:01 PM PDT 24 9309054304 ps
T794 /workspace/coverage/default/34.sram_ctrl_smoke.2699052662 Jun 25 04:50:01 PM PDT 24 Jun 25 04:50:11 PM PDT 24 473310701 ps
T795 /workspace/coverage/default/36.sram_ctrl_partial_access.872107807 Jun 25 04:50:09 PM PDT 24 Jun 25 04:50:30 PM PDT 24 911424559 ps
T796 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1926655559 Jun 25 04:48:36 PM PDT 24 Jun 25 04:57:40 PM PDT 24 55554163225 ps
T797 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2253434234 Jun 25 04:48:38 PM PDT 24 Jun 25 04:49:10 PM PDT 24 1817656847 ps
T798 /workspace/coverage/default/12.sram_ctrl_max_throughput.2279161160 Jun 25 04:48:49 PM PDT 24 Jun 25 04:49:16 PM PDT 24 700581557 ps
T799 /workspace/coverage/default/10.sram_ctrl_multiple_keys.287795241 Jun 25 04:48:46 PM PDT 24 Jun 25 05:06:35 PM PDT 24 297222880730 ps
T800 /workspace/coverage/default/39.sram_ctrl_smoke.605066023 Jun 25 04:50:29 PM PDT 24 Jun 25 04:50:38 PM PDT 24 851344558 ps
T801 /workspace/coverage/default/0.sram_ctrl_stress_all.2697222683 Jun 25 04:48:43 PM PDT 24 Jun 25 07:13:27 PM PDT 24 1176465681273 ps
T802 /workspace/coverage/default/31.sram_ctrl_mem_walk.1821731320 Jun 25 04:49:52 PM PDT 24 Jun 25 04:52:58 PM PDT 24 37430488518 ps
T803 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3209265645 Jun 25 04:50:19 PM PDT 24 Jun 25 04:57:26 PM PDT 24 38029167442 ps
T804 /workspace/coverage/default/43.sram_ctrl_smoke.3042660702 Jun 25 04:50:56 PM PDT 24 Jun 25 04:51:36 PM PDT 24 2626028969 ps
T805 /workspace/coverage/default/7.sram_ctrl_multiple_keys.4082960394 Jun 25 04:48:52 PM PDT 24 Jun 25 05:16:07 PM PDT 24 94769997979 ps
T806 /workspace/coverage/default/47.sram_ctrl_smoke.2513485952 Jun 25 04:51:23 PM PDT 24 Jun 25 04:51:36 PM PDT 24 1407143393 ps
T807 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.599993729 Jun 25 04:48:40 PM PDT 24 Jun 25 04:51:39 PM PDT 24 72821793620 ps
T808 /workspace/coverage/default/37.sram_ctrl_lc_escalation.4078653834 Jun 25 04:50:19 PM PDT 24 Jun 25 04:50:46 PM PDT 24 4183485467 ps
T809 /workspace/coverage/default/35.sram_ctrl_multiple_keys.3928879471 Jun 25 04:50:05 PM PDT 24 Jun 25 05:08:59 PM PDT 24 219526661891 ps
T810 /workspace/coverage/default/46.sram_ctrl_mem_walk.2152767847 Jun 25 04:51:11 PM PDT 24 Jun 25 04:53:49 PM PDT 24 2713176309 ps
T811 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2362779159 Jun 25 04:49:34 PM PDT 24 Jun 25 04:57:42 PM PDT 24 120549347956 ps
T812 /workspace/coverage/default/5.sram_ctrl_stress_all.2439945749 Jun 25 04:48:38 PM PDT 24 Jun 25 06:41:13 PM PDT 24 100842367182 ps
T813 /workspace/coverage/default/2.sram_ctrl_stress_all.1985861923 Jun 25 04:48:48 PM PDT 24 Jun 25 05:28:46 PM PDT 24 177150817463 ps
T814 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.98753310 Jun 25 04:49:25 PM PDT 24 Jun 25 04:51:44 PM PDT 24 17490115774 ps
T815 /workspace/coverage/default/42.sram_ctrl_regwen.2075581516 Jun 25 04:50:48 PM PDT 24 Jun 25 05:18:24 PM PDT 24 14435934714 ps
T816 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2603199774 Jun 25 04:49:24 PM PDT 24 Jun 25 04:51:18 PM PDT 24 1536270318 ps
T817 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3132621651 Jun 25 04:51:03 PM PDT 24 Jun 25 04:56:44 PM PDT 24 53641130436 ps
T818 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.322045381 Jun 25 04:50:37 PM PDT 24 Jun 25 05:12:16 PM PDT 24 52086996917 ps
T819 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2219479074 Jun 25 04:49:40 PM PDT 24 Jun 25 04:52:17 PM PDT 24 5127729425 ps
T820 /workspace/coverage/default/17.sram_ctrl_executable.1100660262 Jun 25 04:49:20 PM PDT 24 Jun 25 05:05:17 PM PDT 24 5803252277 ps
T821 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2724749006 Jun 25 04:51:06 PM PDT 24 Jun 25 04:52:16 PM PDT 24 188343795031 ps
T822 /workspace/coverage/default/35.sram_ctrl_regwen.522496552 Jun 25 04:50:14 PM PDT 24 Jun 25 04:52:48 PM PDT 24 690857491 ps
T823 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2694317704 Jun 25 04:49:43 PM PDT 24 Jun 25 04:50:51 PM PDT 24 1023064071 ps
T824 /workspace/coverage/default/43.sram_ctrl_mem_walk.3830276281 Jun 25 04:51:02 PM PDT 24 Jun 25 04:53:58 PM PDT 24 10767401722 ps
T825 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2540724642 Jun 25 04:50:33 PM PDT 24 Jun 25 04:59:16 PM PDT 24 234457770772 ps
T826 /workspace/coverage/default/7.sram_ctrl_partial_access.2679486368 Jun 25 04:48:50 PM PDT 24 Jun 25 04:50:28 PM PDT 24 851743941 ps
T827 /workspace/coverage/default/22.sram_ctrl_executable.2750417294 Jun 25 04:49:34 PM PDT 24 Jun 25 05:06:17 PM PDT 24 4172699754 ps
T828 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1427984260 Jun 25 04:49:19 PM PDT 24 Jun 25 04:49:41 PM PDT 24 8858169250 ps
T829 /workspace/coverage/default/9.sram_ctrl_alert_test.1956737041 Jun 25 04:48:51 PM PDT 24 Jun 25 04:49:04 PM PDT 24 44759588 ps
T830 /workspace/coverage/default/14.sram_ctrl_ram_cfg.2951272029 Jun 25 04:48:47 PM PDT 24 Jun 25 04:49:04 PM PDT 24 1413716455 ps
T831 /workspace/coverage/default/46.sram_ctrl_regwen.3405910086 Jun 25 04:51:11 PM PDT 24 Jun 25 05:04:39 PM PDT 24 16606130273 ps
T832 /workspace/coverage/default/12.sram_ctrl_smoke.4201264000 Jun 25 04:48:46 PM PDT 24 Jun 25 04:51:32 PM PDT 24 953045276 ps
T833 /workspace/coverage/default/48.sram_ctrl_lc_escalation.761004384 Jun 25 04:51:29 PM PDT 24 Jun 25 04:53:12 PM PDT 24 16858011310 ps
T834 /workspace/coverage/default/44.sram_ctrl_mem_walk.3712044719 Jun 25 04:51:00 PM PDT 24 Jun 25 04:57:02 PM PDT 24 44957049399 ps
T835 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1156387968 Jun 25 04:49:23 PM PDT 24 Jun 25 04:49:55 PM PDT 24 1472691749 ps
T836 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2781575421 Jun 25 04:48:49 PM PDT 24 Jun 25 04:50:36 PM PDT 24 53814963582 ps
T837 /workspace/coverage/default/39.sram_ctrl_ram_cfg.4185570742 Jun 25 04:50:32 PM PDT 24 Jun 25 04:50:36 PM PDT 24 1357111397 ps
T838 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2184032334 Jun 25 04:49:09 PM PDT 24 Jun 25 04:50:39 PM PDT 24 10476431956 ps
T839 /workspace/coverage/default/28.sram_ctrl_partial_access.936251999 Jun 25 04:49:37 PM PDT 24 Jun 25 04:50:01 PM PDT 24 3848420405 ps
T840 /workspace/coverage/default/38.sram_ctrl_smoke.376756921 Jun 25 04:50:19 PM PDT 24 Jun 25 04:50:38 PM PDT 24 2265800945 ps
T841 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.987750580 Jun 25 04:48:42 PM PDT 24 Jun 25 05:26:20 PM PDT 24 48266628278 ps
T842 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2287571942 Jun 25 04:50:55 PM PDT 24 Jun 25 04:55:36 PM PDT 24 5150777146 ps
T843 /workspace/coverage/default/48.sram_ctrl_max_throughput.4167940182 Jun 25 04:51:32 PM PDT 24 Jun 25 04:51:39 PM PDT 24 2665581237 ps
T844 /workspace/coverage/default/41.sram_ctrl_partial_access.2972376414 Jun 25 04:50:38 PM PDT 24 Jun 25 04:50:59 PM PDT 24 5209175479 ps
T845 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2255347338 Jun 25 04:49:17 PM PDT 24 Jun 25 04:54:02 PM PDT 24 21250087726 ps
T846 /workspace/coverage/default/46.sram_ctrl_ram_cfg.418337935 Jun 25 04:51:13 PM PDT 24 Jun 25 04:51:17 PM PDT 24 1245483217 ps
T847 /workspace/coverage/default/10.sram_ctrl_stress_all.1243838097 Jun 25 04:48:48 PM PDT 24 Jun 25 06:00:13 PM PDT 24 350315434142 ps
T848 /workspace/coverage/default/46.sram_ctrl_bijection.4115088763 Jun 25 04:51:12 PM PDT 24 Jun 25 05:02:13 PM PDT 24 116333161244 ps
T849 /workspace/coverage/default/48.sram_ctrl_partial_access.991989126 Jun 25 04:51:23 PM PDT 24 Jun 25 04:51:34 PM PDT 24 2637991833 ps
T850 /workspace/coverage/default/16.sram_ctrl_lc_escalation.3335524774 Jun 25 04:49:17 PM PDT 24 Jun 25 04:50:02 PM PDT 24 13405133186 ps
T851 /workspace/coverage/default/44.sram_ctrl_lc_escalation.3964763807 Jun 25 04:51:03 PM PDT 24 Jun 25 04:51:20 PM PDT 24 11344102750 ps
T852 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2239052345 Jun 25 04:49:34 PM PDT 24 Jun 25 04:53:19 PM PDT 24 15343210545 ps
T853 /workspace/coverage/default/26.sram_ctrl_regwen.1816262426 Jun 25 04:49:40 PM PDT 24 Jun 25 05:00:34 PM PDT 24 8581788262 ps
T854 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2317119075 Jun 25 04:48:42 PM PDT 24 Jun 25 04:52:02 PM PDT 24 3420803918 ps
T855 /workspace/coverage/default/1.sram_ctrl_partial_access.3741187561 Jun 25 04:48:37 PM PDT 24 Jun 25 04:49:00 PM PDT 24 748477825 ps
T856 /workspace/coverage/default/27.sram_ctrl_stress_all.1447640662 Jun 25 04:49:42 PM PDT 24 Jun 25 05:35:26 PM PDT 24 47460205471 ps
T857 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2558044821 Jun 25 04:51:03 PM PDT 24 Jun 25 04:54:01 PM PDT 24 6545007634 ps
T858 /workspace/coverage/default/18.sram_ctrl_multiple_keys.1978434777 Jun 25 04:49:23 PM PDT 24 Jun 25 04:54:41 PM PDT 24 5689035008 ps
T859 /workspace/coverage/default/25.sram_ctrl_partial_access.814343985 Jun 25 04:49:31 PM PDT 24 Jun 25 04:49:40 PM PDT 24 1664415976 ps
T860 /workspace/coverage/default/32.sram_ctrl_multiple_keys.3778274501 Jun 25 04:49:52 PM PDT 24 Jun 25 05:05:43 PM PDT 24 16747832804 ps
T861 /workspace/coverage/default/21.sram_ctrl_bijection.1525384212 Jun 25 04:49:27 PM PDT 24 Jun 25 05:27:53 PM PDT 24 33162290615 ps
T862 /workspace/coverage/default/36.sram_ctrl_smoke.330460766 Jun 25 04:50:09 PM PDT 24 Jun 25 04:50:31 PM PDT 24 3995353176 ps
T863 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.830424138 Jun 25 04:48:50 PM PDT 24 Jun 25 04:50:41 PM PDT 24 5086843842 ps
T864 /workspace/coverage/default/24.sram_ctrl_alert_test.4291614152 Jun 25 04:49:34 PM PDT 24 Jun 25 04:49:37 PM PDT 24 15439977 ps
T865 /workspace/coverage/default/24.sram_ctrl_multiple_keys.3744563152 Jun 25 04:49:39 PM PDT 24 Jun 25 05:14:16 PM PDT 24 30222975004 ps
T99 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4054244099 Jun 25 04:49:47 PM PDT 24 Jun 25 04:51:03 PM PDT 24 1479945970 ps
T866 /workspace/coverage/default/2.sram_ctrl_smoke.2604259331 Jun 25 04:48:48 PM PDT 24 Jun 25 04:49:19 PM PDT 24 1250814438 ps
T867 /workspace/coverage/default/11.sram_ctrl_stress_all.3451357602 Jun 25 04:49:14 PM PDT 24 Jun 25 05:45:14 PM PDT 24 299590978254 ps
T868 /workspace/coverage/default/17.sram_ctrl_multiple_keys.3335357201 Jun 25 04:49:05 PM PDT 24 Jun 25 04:53:38 PM PDT 24 12297048213 ps
T869 /workspace/coverage/default/15.sram_ctrl_regwen.3075765030 Jun 25 04:49:09 PM PDT 24 Jun 25 05:09:11 PM PDT 24 10493064139 ps
T870 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.56212275 Jun 25 04:49:01 PM PDT 24 Jun 25 04:52:10 PM PDT 24 3937496871 ps
T871 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1637512639 Jun 25 04:48:50 PM PDT 24 Jun 25 05:03:22 PM PDT 24 15486270552 ps
T872 /workspace/coverage/default/5.sram_ctrl_regwen.2201983646 Jun 25 04:48:37 PM PDT 24 Jun 25 05:19:10 PM PDT 24 17775457209 ps
T873 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2247271136 Jun 25 04:49:52 PM PDT 24 Jun 25 04:52:49 PM PDT 24 12959890859 ps
T874 /workspace/coverage/default/47.sram_ctrl_max_throughput.36395971 Jun 25 04:51:27 PM PDT 24 Jun 25 04:54:14 PM PDT 24 4499162099 ps
T875 /workspace/coverage/default/38.sram_ctrl_max_throughput.1968655954 Jun 25 04:50:21 PM PDT 24 Jun 25 04:52:23 PM PDT 24 10728326825 ps
T876 /workspace/coverage/default/41.sram_ctrl_max_throughput.230106717 Jun 25 04:50:38 PM PDT 24 Jun 25 04:50:53 PM PDT 24 2761062446 ps
T877 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4199206274 Jun 25 04:49:38 PM PDT 24 Jun 25 04:49:50 PM PDT 24 184019003 ps
T878 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.758979661 Jun 25 04:49:16 PM PDT 24 Jun 25 04:49:48 PM PDT 24 1484861605 ps
T879 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2771910870 Jun 25 04:51:31 PM PDT 24 Jun 25 04:53:44 PM PDT 24 2613102584 ps
T880 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3869095146 Jun 25 04:50:40 PM PDT 24 Jun 25 04:51:42 PM PDT 24 36177159757 ps
T881 /workspace/coverage/default/46.sram_ctrl_alert_test.1268251496 Jun 25 04:51:22 PM PDT 24 Jun 25 04:51:23 PM PDT 24 14874998 ps
T882 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2758353822 Jun 25 04:48:46 PM PDT 24 Jun 25 04:49:04 PM PDT 24 1541319478 ps
T883 /workspace/coverage/default/21.sram_ctrl_partial_access.2642189514 Jun 25 04:49:28 PM PDT 24 Jun 25 04:51:35 PM PDT 24 2052434337 ps
T884 /workspace/coverage/default/10.sram_ctrl_partial_access.3169337263 Jun 25 04:48:50 PM PDT 24 Jun 25 04:49:26 PM PDT 24 7015559097 ps
T885 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4233293939 Jun 25 04:51:33 PM PDT 24 Jun 25 04:56:17 PM PDT 24 220320597986 ps
T886 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2671335108 Jun 25 04:48:47 PM PDT 24 Jun 25 04:49:04 PM PDT 24 354577598 ps
T887 /workspace/coverage/default/43.sram_ctrl_partial_access.25182771 Jun 25 04:50:57 PM PDT 24 Jun 25 04:52:14 PM PDT 24 1663701386 ps
T888 /workspace/coverage/default/36.sram_ctrl_multiple_keys.408448953 Jun 25 04:50:09 PM PDT 24 Jun 25 05:07:45 PM PDT 24 59653135220 ps
T889 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1378338510 Jun 25 04:48:45 PM PDT 24 Jun 25 04:52:34 PM PDT 24 11610764655 ps
T890 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1412586776 Jun 25 04:51:02 PM PDT 24 Jun 25 04:58:13 PM PDT 24 13022210465 ps
T891 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1231203093 Jun 25 04:48:34 PM PDT 24 Jun 25 04:55:55 PM PDT 24 13574026022 ps
T892 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2329208832 Jun 25 04:49:25 PM PDT 24 Jun 25 04:51:19 PM PDT 24 8810565577 ps
T893 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3283647509 Jun 25 04:48:49 PM PDT 24 Jun 25 04:50:26 PM PDT 24 10162013698 ps
T894 /workspace/coverage/default/41.sram_ctrl_alert_test.3952793684 Jun 25 04:50:47 PM PDT 24 Jun 25 04:50:49 PM PDT 24 86537485 ps
T895 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3453528801 Jun 25 04:49:39 PM PDT 24 Jun 25 04:56:27 PM PDT 24 32993064917 ps
T896 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3882614676 Jun 25 04:48:58 PM PDT 24 Jun 25 04:51:11 PM PDT 24 6841837372 ps
T897 /workspace/coverage/default/45.sram_ctrl_executable.1087724587 Jun 25 04:51:04 PM PDT 24 Jun 25 04:55:27 PM PDT 24 5485371841 ps
T898 /workspace/coverage/default/22.sram_ctrl_multiple_keys.1816467456 Jun 25 04:49:22 PM PDT 24 Jun 25 05:11:57 PM PDT 24 24952239445 ps
T899 /workspace/coverage/default/45.sram_ctrl_partial_access.1538032175 Jun 25 04:51:04 PM PDT 24 Jun 25 04:53:30 PM PDT 24 1834525896 ps
T900 /workspace/coverage/default/6.sram_ctrl_partial_access.3976058275 Jun 25 04:49:02 PM PDT 24 Jun 25 04:51:45 PM PDT 24 5163212958 ps
T901 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1790361933 Jun 25 04:49:17 PM PDT 24 Jun 25 04:49:21 PM PDT 24 347345774 ps
T902 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.353464913 Jun 25 04:49:41 PM PDT 24 Jun 25 04:54:06 PM PDT 24 9335244675 ps
T903 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.734583964 Jun 25 04:48:40 PM PDT 24 Jun 25 05:06:03 PM PDT 24 44268567278 ps
T904 /workspace/coverage/default/12.sram_ctrl_regwen.2861421331 Jun 25 04:48:47 PM PDT 24 Jun 25 05:09:12 PM PDT 24 114755040377 ps
T905 /workspace/coverage/default/24.sram_ctrl_partial_access.441554392 Jun 25 04:49:36 PM PDT 24 Jun 25 04:49:56 PM PDT 24 2959392521 ps
T906 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.71875841 Jun 25 04:50:08 PM PDT 24 Jun 25 05:05:40 PM PDT 24 11372123706 ps
T907 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.94212388 Jun 25 04:51:40 PM PDT 24 Jun 25 04:53:59 PM PDT 24 4549504979 ps
T908 /workspace/coverage/default/31.sram_ctrl_partial_access.4077847850 Jun 25 04:49:46 PM PDT 24 Jun 25 04:52:08 PM PDT 24 959455672 ps
T909 /workspace/coverage/default/19.sram_ctrl_partial_access.838862839 Jun 25 04:49:17 PM PDT 24 Jun 25 04:49:42 PM PDT 24 11226709056 ps
T910 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3394439145 Jun 25 04:49:51 PM PDT 24 Jun 25 04:51:40 PM PDT 24 3134065188 ps
T911 /workspace/coverage/default/33.sram_ctrl_multiple_keys.2733430080 Jun 25 04:49:54 PM PDT 24 Jun 25 05:01:50 PM PDT 24 27346666755 ps
T912 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2550673827 Jun 25 04:50:40 PM PDT 24 Jun 25 04:50:46 PM PDT 24 5604590282 ps
T913 /workspace/coverage/default/32.sram_ctrl_ram_cfg.832385719 Jun 25 04:49:54 PM PDT 24 Jun 25 04:49:58 PM PDT 24 466015745 ps
T914 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2534203847 Jun 25 04:49:09 PM PDT 24 Jun 25 04:49:57 PM PDT 24 30092324197 ps
T915 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2659228964 Jun 25 04:49:15 PM PDT 24 Jun 25 04:51:54 PM PDT 24 4818486644 ps
T916 /workspace/coverage/default/44.sram_ctrl_max_throughput.3968257687 Jun 25 04:51:13 PM PDT 24 Jun 25 04:53:36 PM PDT 24 1598888649 ps
T917 /workspace/coverage/default/7.sram_ctrl_stress_all.2363030833 Jun 25 04:49:05 PM PDT 24 Jun 25 07:15:33 PM PDT 24 323134196367 ps
T918 /workspace/coverage/default/46.sram_ctrl_max_throughput.1544724840 Jun 25 04:51:14 PM PDT 24 Jun 25 04:51:50 PM PDT 24 2999149278 ps
T919 /workspace/coverage/default/19.sram_ctrl_multiple_keys.865117841 Jun 25 04:49:21 PM PDT 24 Jun 25 05:16:15 PM PDT 24 22884703838 ps
T920 /workspace/coverage/default/33.sram_ctrl_executable.53567439 Jun 25 04:50:02 PM PDT 24 Jun 25 04:59:04 PM PDT 24 35555339537 ps
T921 /workspace/coverage/default/12.sram_ctrl_mem_walk.862208567 Jun 25 04:48:53 PM PDT 24 Jun 25 04:52:09 PM PDT 24 41321493485 ps
T922 /workspace/coverage/default/46.sram_ctrl_smoke.2049039963 Jun 25 04:51:13 PM PDT 24 Jun 25 04:52:01 PM PDT 24 3126310521 ps
T100 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1805231450 Jun 25 04:49:18 PM PDT 24 Jun 25 04:50:37 PM PDT 24 1421299025 ps
T923 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4108425281 Jun 25 04:48:34 PM PDT 24 Jun 25 04:53:43 PM PDT 24 13717587136 ps
T924 /workspace/coverage/default/1.sram_ctrl_mem_walk.2272691203 Jun 25 04:48:49 PM PDT 24 Jun 25 04:51:15 PM PDT 24 8231181542 ps
T925 /workspace/coverage/default/20.sram_ctrl_smoke.1550767224 Jun 25 04:49:28 PM PDT 24 Jun 25 04:50:22 PM PDT 24 3079295482 ps
T926 /workspace/coverage/default/11.sram_ctrl_max_throughput.3229401958 Jun 25 04:48:47 PM PDT 24 Jun 25 04:49:39 PM PDT 24 1561161258 ps
T927 /workspace/coverage/default/7.sram_ctrl_max_throughput.2266706396 Jun 25 04:48:44 PM PDT 24 Jun 25 04:49:33 PM PDT 24 2864600530 ps
T928 /workspace/coverage/default/0.sram_ctrl_executable.3949427638 Jun 25 04:48:27 PM PDT 24 Jun 25 04:50:47 PM PDT 24 2581587624 ps
T929 /workspace/coverage/default/32.sram_ctrl_bijection.3722656339 Jun 25 04:49:52 PM PDT 24 Jun 25 05:03:36 PM PDT 24 97023289278 ps
T930 /workspace/coverage/default/15.sram_ctrl_executable.3696400484 Jun 25 04:49:15 PM PDT 24 Jun 25 05:01:19 PM PDT 24 87589280839 ps
T931 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.401912182 Jun 25 04:50:56 PM PDT 24 Jun 25 05:00:16 PM PDT 24 26541903011 ps
T932 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3272805928 Jun 25 04:49:54 PM PDT 24 Jun 25 04:52:53 PM PDT 24 20371735673 ps
T933 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2901865503 Jun 25 04:49:02 PM PDT 24 Jun 25 04:53:59 PM PDT 24 38743448742 ps
T934 /workspace/coverage/default/1.sram_ctrl_executable.2633840124 Jun 25 04:48:35 PM PDT 24 Jun 25 05:02:29 PM PDT 24 42767046287 ps
T935 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1953680850 Jun 25 04:49:33 PM PDT 24 Jun 25 04:50:15 PM PDT 24 25733648459 ps
T936 /workspace/coverage/default/32.sram_ctrl_lc_escalation.173213545 Jun 25 04:49:54 PM PDT 24 Jun 25 04:50:52 PM PDT 24 38894636367 ps
T937 /workspace/coverage/default/43.sram_ctrl_regwen.1150089787 Jun 25 04:50:54 PM PDT 24 Jun 25 04:55:31 PM PDT 24 33107236462 ps
T938 /workspace/coverage/default/30.sram_ctrl_bijection.535472860 Jun 25 04:49:40 PM PDT 24 Jun 25 05:23:54 PM PDT 24 171605799779 ps
T939 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3963219095 Jun 25 04:51:23 PM PDT 24 Jun 25 05:09:23 PM PDT 24 58284872614 ps
T72 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3574144403 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:41 PM PDT 24 42835480 ps
T69 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.913868715 Jun 25 04:47:53 PM PDT 24 Jun 25 04:48:00 PM PDT 24 471397156 ps
T73 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1322933541 Jun 25 04:47:49 PM PDT 24 Jun 25 04:47:53 PM PDT 24 48683678 ps
T109 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2331761600 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:45 PM PDT 24 28755739 ps
T940 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.163340466 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:04 PM PDT 24 1435649212 ps
T82 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3614883566 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:54 PM PDT 24 29431905116 ps
T83 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.479661584 Jun 25 04:47:49 PM PDT 24 Jun 25 04:47:52 PM PDT 24 13260599 ps
T84 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3463546709 Jun 25 04:48:00 PM PDT 24 Jun 25 04:48:04 PM PDT 24 12156061 ps
T85 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4278461675 Jun 25 04:47:40 PM PDT 24 Jun 25 04:48:13 PM PDT 24 3777928029 ps
T941 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4050478567 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:02 PM PDT 24 109592952 ps
T86 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.679161153 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:17 PM PDT 24 7655206989 ps
T87 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2984413280 Jun 25 04:47:43 PM PDT 24 Jun 25 04:47:47 PM PDT 24 55431099 ps
T88 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3513769258 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:24 PM PDT 24 30847987748 ps
T942 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1186684956 Jun 25 04:47:53 PM PDT 24 Jun 25 04:48:02 PM PDT 24 405264932 ps
T110 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2860092145 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:00 PM PDT 24 23034604 ps
T70 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.714457042 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:04 PM PDT 24 687668930 ps
T943 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2069245863 Jun 25 04:47:52 PM PDT 24 Jun 25 04:47:56 PM PDT 24 46841161 ps
T944 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3255253391 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:40 PM PDT 24 48145734 ps
T945 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.521013385 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:55 PM PDT 24 3523758350 ps
T111 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3159028685 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:40 PM PDT 24 43787203 ps
T89 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4267787529 Jun 25 04:47:38 PM PDT 24 Jun 25 04:48:41 PM PDT 24 29440050060 ps
T946 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.855394016 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:44 PM PDT 24 31371705 ps
T947 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1309739864 Jun 25 04:47:59 PM PDT 24 Jun 25 04:48:30 PM PDT 24 3911003015 ps
T71 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2920883007 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:43 PM PDT 24 606191090 ps
T948 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2649027619 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:46 PM PDT 24 267462889 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1677539634 Jun 25 04:47:39 PM PDT 24 Jun 25 04:47:44 PM PDT 24 52444335 ps
T133 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1865532010 Jun 25 04:47:47 PM PDT 24 Jun 25 04:47:51 PM PDT 24 1146942153 ps
T950 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3030707783 Jun 25 04:47:54 PM PDT 24 Jun 25 04:47:59 PM PDT 24 32663980 ps
T134 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1871989111 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:52 PM PDT 24 152373462 ps
T951 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3312509884 Jun 25 04:47:50 PM PDT 24 Jun 25 04:47:55 PM PDT 24 130989968 ps
T952 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1590123006 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:58 PM PDT 24 356279434 ps
T953 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1428294847 Jun 25 04:47:39 PM PDT 24 Jun 25 04:47:45 PM PDT 24 248700442 ps
T90 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1053877207 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:44 PM PDT 24 50332125 ps
T954 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3188130531 Jun 25 04:47:46 PM PDT 24 Jun 25 04:47:52 PM PDT 24 1553273408 ps
T91 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.935237974 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:57 PM PDT 24 28140441364 ps
T955 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3622608447 Jun 25 04:47:41 PM PDT 24 Jun 25 04:47:49 PM PDT 24 119150356 ps
T956 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3396031329 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:05 PM PDT 24 1150288890 ps
T957 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3992357444 Jun 25 04:47:52 PM PDT 24 Jun 25 04:47:56 PM PDT 24 88940153 ps
T958 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.999379111 Jun 25 04:47:43 PM PDT 24 Jun 25 04:48:39 PM PDT 24 7416672718 ps
T959 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1992014148 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:50 PM PDT 24 17175319 ps
T960 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.654020712 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:45 PM PDT 24 30694221 ps
T961 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3037715844 Jun 25 04:47:53 PM PDT 24 Jun 25 04:47:59 PM PDT 24 25838984 ps
T962 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4029245957 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:58 PM PDT 24 71596474 ps
T963 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3989139002 Jun 25 04:47:50 PM PDT 24 Jun 25 04:47:54 PM PDT 24 14825321 ps
T964 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1279275102 Jun 25 04:47:50 PM PDT 24 Jun 25 04:47:53 PM PDT 24 16143907 ps
T965 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2273695980 Jun 25 04:47:36 PM PDT 24 Jun 25 04:47:38 PM PDT 24 88162422 ps
T135 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3160853452 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:45 PM PDT 24 832605859 ps
T966 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1315274342 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:41 PM PDT 24 13599165 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2170676174 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:43 PM PDT 24 65341979 ps
T968 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3841722647 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:41 PM PDT 24 87679199 ps
T969 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1705921946 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:52 PM PDT 24 85422271 ps
T970 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2464361694 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:42 PM PDT 24 348913522 ps
T971 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2914987803 Jun 25 04:47:38 PM PDT 24 Jun 25 04:48:11 PM PDT 24 7798086998 ps
T92 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4244173978 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:18 PM PDT 24 3893258544 ps
T93 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3291681439 Jun 25 04:47:39 PM PDT 24 Jun 25 04:47:43 PM PDT 24 17386234 ps
T972 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3660872130 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:04 PM PDT 24 534738468 ps
T973 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2906595243 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:40 PM PDT 24 40568445 ps
T974 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3043339819 Jun 25 04:47:47 PM PDT 24 Jun 25 04:47:53 PM PDT 24 421076888 ps
T975 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1283892892 Jun 25 04:47:37 PM PDT 24 Jun 25 04:48:07 PM PDT 24 3855852135 ps
T101 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2075944377 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:39 PM PDT 24 17157650 ps
T136 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1629842270 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:57 PM PDT 24 247386057 ps
T137 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3178289421 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:58 PM PDT 24 2452736426 ps
T138 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2971784463 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:51 PM PDT 24 295915387 ps
T976 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3692388313 Jun 25 04:47:40 PM PDT 24 Jun 25 04:47:45 PM PDT 24 45408132 ps
T140 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4227532675 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:04 PM PDT 24 788592554 ps
T977 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.561969653 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:24 PM PDT 24 15382877771 ps
T978 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.916374546 Jun 25 04:47:47 PM PDT 24 Jun 25 04:47:50 PM PDT 24 80831109 ps
T102 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1002698693 Jun 25 04:47:38 PM PDT 24 Jun 25 04:48:35 PM PDT 24 78369757884 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2089680108 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:55 PM PDT 24 137690085 ps
T980 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.337885231 Jun 25 04:47:37 PM PDT 24 Jun 25 04:47:40 PM PDT 24 53710376 ps
T981 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1033862631 Jun 25 04:47:36 PM PDT 24 Jun 25 04:47:39 PM PDT 24 507535464 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.346586560 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:43 PM PDT 24 61517771 ps
T983 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1596482125 Jun 25 04:48:00 PM PDT 24 Jun 25 04:48:04 PM PDT 24 56450948 ps
T984 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.400471954 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:50 PM PDT 24 51764189 ps
T985 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2661206708 Jun 25 04:47:41 PM PDT 24 Jun 25 04:47:45 PM PDT 24 40763002 ps
T986 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3136430924 Jun 25 04:47:43 PM PDT 24 Jun 25 04:47:47 PM PDT 24 14411477 ps
T987 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1478334731 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:54 PM PDT 24 28212362848 ps
T988 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1821038389 Jun 25 04:47:49 PM PDT 24 Jun 25 04:47:55 PM PDT 24 463401004 ps
T989 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2363396936 Jun 25 04:47:51 PM PDT 24 Jun 25 04:47:59 PM PDT 24 736000700 ps
T990 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1808334344 Jun 25 04:47:47 PM PDT 24 Jun 25 04:47:49 PM PDT 24 13871991 ps
T141 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2368178435 Jun 25 04:47:49 PM PDT 24 Jun 25 04:47:53 PM PDT 24 175074430 ps
T991 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3619974880 Jun 25 04:47:43 PM PDT 24 Jun 25 04:47:47 PM PDT 24 59541285 ps
T992 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.853997186 Jun 25 04:47:39 PM PDT 24 Jun 25 04:47:45 PM PDT 24 274069834 ps
T993 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1909792264 Jun 25 04:47:40 PM PDT 24 Jun 25 04:48:38 PM PDT 24 7612950947 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.749401340 Jun 25 04:47:36 PM PDT 24 Jun 25 04:47:37 PM PDT 24 38808241 ps
T995 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.821646744 Jun 25 04:47:41 PM PDT 24 Jun 25 04:47:47 PM PDT 24 1187059528 ps
T996 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1758791001 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:00 PM PDT 24 19805245 ps
T997 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3197517119 Jun 25 04:47:48 PM PDT 24 Jun 25 04:47:50 PM PDT 24 16838442 ps
T998 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2514569892 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:01 PM PDT 24 52890291 ps
T999 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3440064320 Jun 25 04:47:46 PM PDT 24 Jun 25 04:47:52 PM PDT 24 346439400 ps
T1000 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3657532804 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:41 PM PDT 24 22133470 ps
T1001 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3596648869 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:30 PM PDT 24 15380498990 ps
T1002 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.856860921 Jun 25 04:47:53 PM PDT 24 Jun 25 04:47:58 PM PDT 24 14163109 ps
T1003 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1579009883 Jun 25 04:47:50 PM PDT 24 Jun 25 04:47:54 PM PDT 24 16045571 ps
T1004 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2268068246 Jun 25 04:47:38 PM PDT 24 Jun 25 04:47:41 PM PDT 24 42424025 ps
T103 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2669579372 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:00 PM PDT 24 47208980 ps
T1005 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.544264189 Jun 25 04:47:49 PM PDT 24 Jun 25 04:47:56 PM PDT 24 687647742 ps
T1006 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.893557105 Jun 25 04:47:36 PM PDT 24 Jun 25 04:47:38 PM PDT 24 26579493 ps
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