Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	324679576	1			T1	14454		T2	231578		T3	159532
instr_valid_dis	284355662	1			T1	14454		T2	231578		T3	159532
instr_en	28380863	1			T4	20310		T27	9616		T28	65314

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	16055630	1			T4	46060		T27	38278		T28	36820
sram_ifetch_valid_disable	277089478	1			T1	14454		T2	231578		T3	159532
sram_ifetch_enable	31534468	1			T4	163720		T5	33454		T27	61020

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	324679576	1			T1	14454		T2	231578		T3	159532
hw_debug_en_valid_off	280883698	1			T1	14454		T2	231578		T3	159532
hw_debug_en_on	25868016	1			T4	137688		T5	13968		T27	56704

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	277089478	1			T1	14454		T2	231578		T3	159532
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	263295668	1			T1	14454		T2	231578		T3	159532
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9908819	1			T4	2766		T28	12352		T21	203448
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6515656	1			T4	27084		T27	28662		T66	85088
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4641386	1			T4	27084		T27	28662		T66	85088
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1437840	1			T135	17852		T9	45872		T24	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7023920	1			T4	18976		T27	9616		T28	36820
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1824990	1			T4	18976		T66	74004		T132	40860
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4327064	1			T27	9616		T28	36820		T132	70480
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8965622	1			T4	83334		T5	13968		T27	28158
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3615110	1			T4	83334		T5	13968		T27	28158
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3552046	1			T21	162626		T135	34972		T133	35022

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11836576	1			T4	17544		T28	16142		T21	187456
lc_exec_en	9878474	1			T4	35378		T27	18930		T21	60950
valid_exec_dis	276211422	1			T1	14454		T2	231578		T3	159532
invalid_exec_dis	47590098	1			T4	209780		T5	33454		T27	99298