Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	132274304	1			T1	1336		T2	105143		T3	72564
triple_byte_access	2797564	1			T1	1178		T2	2167		T3	1430
halfword_access	4294020	1			T1	1762		T2	3129		T3	2179
byte_access	5997196	1			T1	2357		T2	4225		T3	2861
zero_access	1806192	1			T1	594		T2	1125		T3	732

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73399282

1

T1

3614

T2

58016

T3

39608

auto[1]

73769994

1

T1

3613

T2

57773

T3

40158

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	65818281	1			T1	663		T2	52619		T3	36052
auto[0]	triple_byte_access	1336810	1			T1	598		T2	1087		T3	713
auto[0]	halfword_access	2099450	1			T1	872		T2	1593		T3	1027
auto[0]	byte_access	3070088	1			T1	1186		T2	2151		T3	1452
auto[0]	zero_access	1074653	1			T1	295		T2	566		T3	364
auto[1]	word_access	66456023	1			T1	673		T2	52524		T3	36512
auto[1]	triple_byte_access	1460754	1			T1	580		T2	1080		T3	717
auto[1]	halfword_access	2194570	1			T1	890		T2	1536		T3	1152
auto[1]	byte_access	2927108	1			T1	1171		T2	2074		T3	1409
auto[1]	zero_access	731539	1			T1	299		T2	559		T3	368