| T797 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2524032449 |
|
|
Jul 01 05:45:44 PM PDT 24 |
Jul 01 06:10:47 PM PDT 24 |
49719097864 ps |
| T798 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1152197401 |
|
|
Jul 01 05:44:01 PM PDT 24 |
Jul 01 06:06:18 PM PDT 24 |
9280009109 ps |
| T799 |
/workspace/coverage/default/21.sram_ctrl_bijection.3489057085 |
|
|
Jul 01 05:41:51 PM PDT 24 |
Jul 01 06:00:56 PM PDT 24 |
16689988696 ps |
| T800 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1551329588 |
|
|
Jul 01 05:45:56 PM PDT 24 |
Jul 01 05:48:42 PM PDT 24 |
22257466796 ps |
| T801 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3624003916 |
|
|
Jul 01 05:42:37 PM PDT 24 |
Jul 01 05:45:09 PM PDT 24 |
2860166893 ps |
| T802 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3620543455 |
|
|
Jul 01 05:40:14 PM PDT 24 |
Jul 01 05:45:06 PM PDT 24 |
10504036975 ps |
| T803 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3865323498 |
|
|
Jul 01 05:40:35 PM PDT 24 |
Jul 01 05:41:18 PM PDT 24 |
3438385729 ps |
| T804 |
/workspace/coverage/default/9.sram_ctrl_smoke.2428392354 |
|
|
Jul 01 05:40:29 PM PDT 24 |
Jul 01 05:40:59 PM PDT 24 |
11612345812 ps |
| T805 |
/workspace/coverage/default/14.sram_ctrl_regwen.665292925 |
|
|
Jul 01 05:41:01 PM PDT 24 |
Jul 01 05:49:54 PM PDT 24 |
31411009088 ps |
| T806 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3921248009 |
|
|
Jul 01 05:42:29 PM PDT 24 |
Jul 01 05:52:23 PM PDT 24 |
21090317644 ps |
| T807 |
/workspace/coverage/default/18.sram_ctrl_executable.1641541020 |
|
|
Jul 01 05:41:25 PM PDT 24 |
Jul 01 05:46:01 PM PDT 24 |
45900895157 ps |
| T808 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2099839734 |
|
|
Jul 01 05:43:44 PM PDT 24 |
Jul 01 05:44:11 PM PDT 24 |
733309929 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.204130410 |
|
|
Jul 01 05:42:31 PM PDT 24 |
Jul 01 05:42:42 PM PDT 24 |
2933982559 ps |
| T810 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.213880264 |
|
|
Jul 01 05:46:08 PM PDT 24 |
Jul 01 06:06:53 PM PDT 24 |
48282346659 ps |
| T811 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.459085615 |
|
|
Jul 01 05:41:25 PM PDT 24 |
Jul 01 05:51:46 PM PDT 24 |
20959435689 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1037546685 |
|
|
Jul 01 05:45:44 PM PDT 24 |
Jul 01 05:45:57 PM PDT 24 |
4295549601 ps |
| T813 |
/workspace/coverage/default/5.sram_ctrl_bijection.2281285390 |
|
|
Jul 01 05:40:17 PM PDT 24 |
Jul 01 06:20:22 PM PDT 24 |
256107900944 ps |
| T814 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3480647086 |
|
|
Jul 01 05:40:21 PM PDT 24 |
Jul 01 05:41:48 PM PDT 24 |
2978005119 ps |
| T815 |
/workspace/coverage/default/38.sram_ctrl_bijection.617534481 |
|
|
Jul 01 05:45:03 PM PDT 24 |
Jul 01 06:34:18 PM PDT 24 |
347689728640 ps |
| T816 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1161014358 |
|
|
Jul 01 05:40:37 PM PDT 24 |
Jul 01 05:40:53 PM PDT 24 |
32383658 ps |
| T817 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2524042135 |
|
|
Jul 01 05:46:06 PM PDT 24 |
Jul 01 05:46:11 PM PDT 24 |
348113723 ps |
| T818 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2709008155 |
|
|
Jul 01 05:44:57 PM PDT 24 |
Jul 01 05:45:02 PM PDT 24 |
381434563 ps |
| T819 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3649483808 |
|
|
Jul 01 05:46:14 PM PDT 24 |
Jul 01 05:47:11 PM PDT 24 |
31282621081 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1076109694 |
|
|
Jul 01 05:41:21 PM PDT 24 |
Jul 01 05:41:26 PM PDT 24 |
1679285438 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1014432774 |
|
|
Jul 01 05:40:35 PM PDT 24 |
Jul 01 05:41:56 PM PDT 24 |
781119566 ps |
| T822 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2782126118 |
|
|
Jul 01 05:40:15 PM PDT 24 |
Jul 01 05:40:29 PM PDT 24 |
1334480292 ps |
| T823 |
/workspace/coverage/default/42.sram_ctrl_bijection.2216518739 |
|
|
Jul 01 05:45:49 PM PDT 24 |
Jul 01 06:19:31 PM PDT 24 |
313273182218 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3781626482 |
|
|
Jul 01 05:43:38 PM PDT 24 |
Jul 01 05:46:25 PM PDT 24 |
5144763724 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2002626881 |
|
|
Jul 01 05:40:22 PM PDT 24 |
Jul 01 05:40:38 PM PDT 24 |
675532349 ps |
| T826 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.492667075 |
|
|
Jul 01 05:45:18 PM PDT 24 |
Jul 01 05:45:44 PM PDT 24 |
688190462 ps |
| T827 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2510743776 |
|
|
Jul 01 05:43:08 PM PDT 24 |
Jul 01 05:43:58 PM PDT 24 |
3708460351 ps |
| T828 |
/workspace/coverage/default/49.sram_ctrl_regwen.2846749413 |
|
|
Jul 01 05:47:07 PM PDT 24 |
Jul 01 05:47:44 PM PDT 24 |
2343339978 ps |
| T829 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.4171651707 |
|
|
Jul 01 05:40:07 PM PDT 24 |
Jul 01 05:40:22 PM PDT 24 |
7979669230 ps |
| T830 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1962278758 |
|
|
Jul 01 05:40:06 PM PDT 24 |
Jul 01 05:43:22 PM PDT 24 |
30628097405 ps |
| T831 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4089638702 |
|
|
Jul 01 05:46:49 PM PDT 24 |
Jul 01 05:47:07 PM PDT 24 |
1252624310 ps |
| T832 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1543598911 |
|
|
Jul 01 05:40:23 PM PDT 24 |
Jul 01 05:46:19 PM PDT 24 |
5502796484 ps |
| T833 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1140483783 |
|
|
Jul 01 05:41:21 PM PDT 24 |
Jul 01 05:46:43 PM PDT 24 |
22165100349 ps |
| T834 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3624345839 |
|
|
Jul 01 05:40:55 PM PDT 24 |
Jul 01 07:21:19 PM PDT 24 |
1772227462295 ps |
| T835 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3776674763 |
|
|
Jul 01 05:46:55 PM PDT 24 |
Jul 01 05:47:17 PM PDT 24 |
5698567434 ps |
| T836 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3410147954 |
|
|
Jul 01 05:43:09 PM PDT 24 |
Jul 01 07:05:08 PM PDT 24 |
126806986631 ps |
| T837 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2130335277 |
|
|
Jul 01 05:45:50 PM PDT 24 |
Jul 01 05:45:52 PM PDT 24 |
19970111 ps |
| T838 |
/workspace/coverage/default/38.sram_ctrl_regwen.1574952379 |
|
|
Jul 01 05:45:11 PM PDT 24 |
Jul 01 05:55:08 PM PDT 24 |
4399761383 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.274045492 |
|
|
Jul 01 05:42:45 PM PDT 24 |
Jul 01 05:43:57 PM PDT 24 |
5410268809 ps |
| T840 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4047408763 |
|
|
Jul 01 05:40:41 PM PDT 24 |
Jul 01 05:45:25 PM PDT 24 |
4404205158 ps |
| T841 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1039555427 |
|
|
Jul 01 05:41:42 PM PDT 24 |
Jul 01 05:48:10 PM PDT 24 |
31568475922 ps |
| T842 |
/workspace/coverage/default/12.sram_ctrl_regwen.4137708633 |
|
|
Jul 01 05:40:35 PM PDT 24 |
Jul 01 06:04:31 PM PDT 24 |
3397697734 ps |
| T843 |
/workspace/coverage/default/12.sram_ctrl_smoke.1627817121 |
|
|
Jul 01 05:40:38 PM PDT 24 |
Jul 01 05:41:08 PM PDT 24 |
528767404 ps |
| T844 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1029320760 |
|
|
Jul 01 05:40:40 PM PDT 24 |
Jul 01 05:44:48 PM PDT 24 |
12908911243 ps |
| T845 |
/workspace/coverage/default/3.sram_ctrl_bijection.1707374417 |
|
|
Jul 01 05:40:11 PM PDT 24 |
Jul 01 05:48:18 PM PDT 24 |
25526527403 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_smoke.3781487169 |
|
|
Jul 01 05:44:32 PM PDT 24 |
Jul 01 05:44:57 PM PDT 24 |
1622898744 ps |
| T847 |
/workspace/coverage/default/5.sram_ctrl_regwen.3893277537 |
|
|
Jul 01 05:40:13 PM PDT 24 |
Jul 01 05:54:56 PM PDT 24 |
56716998447 ps |
| T848 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1009525795 |
|
|
Jul 01 05:39:59 PM PDT 24 |
Jul 01 05:51:39 PM PDT 24 |
13104712281 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2765994164 |
|
|
Jul 01 05:46:06 PM PDT 24 |
Jul 01 05:46:08 PM PDT 24 |
14254035 ps |
| T850 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2841649517 |
|
|
Jul 01 05:43:43 PM PDT 24 |
Jul 01 06:11:52 PM PDT 24 |
59121325462 ps |
| T851 |
/workspace/coverage/default/7.sram_ctrl_regwen.2598300823 |
|
|
Jul 01 05:40:22 PM PDT 24 |
Jul 01 05:55:55 PM PDT 24 |
10109463795 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.405860417 |
|
|
Jul 01 05:43:39 PM PDT 24 |
Jul 01 05:45:02 PM PDT 24 |
11853228785 ps |
| T853 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3788830625 |
|
|
Jul 01 05:40:05 PM PDT 24 |
Jul 01 05:42:18 PM PDT 24 |
3953111139 ps |
| T854 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3081053251 |
|
|
Jul 01 05:44:43 PM PDT 24 |
Jul 01 05:46:10 PM PDT 24 |
49538873984 ps |
| T855 |
/workspace/coverage/default/29.sram_ctrl_bijection.1575300916 |
|
|
Jul 01 05:43:24 PM PDT 24 |
Jul 01 05:58:05 PM PDT 24 |
74177436432 ps |
| T856 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2950709233 |
|
|
Jul 01 05:43:32 PM PDT 24 |
Jul 01 06:21:13 PM PDT 24 |
62782197512 ps |
| T857 |
/workspace/coverage/default/1.sram_ctrl_smoke.2327926553 |
|
|
Jul 01 05:40:01 PM PDT 24 |
Jul 01 05:40:20 PM PDT 24 |
6366350598 ps |
| T858 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2116582683 |
|
|
Jul 01 05:40:07 PM PDT 24 |
Jul 01 05:40:28 PM PDT 24 |
2239787780 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_smoke.3466921326 |
|
|
Jul 01 05:45:17 PM PDT 24 |
Jul 01 05:45:34 PM PDT 24 |
521992748 ps |
| T860 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2783725433 |
|
|
Jul 01 05:40:30 PM PDT 24 |
Jul 01 05:52:26 PM PDT 24 |
7621092239 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.80416471 |
|
|
Jul 01 05:44:51 PM PDT 24 |
Jul 01 05:45:03 PM PDT 24 |
357171174 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2222291637 |
|
|
Jul 01 05:41:48 PM PDT 24 |
Jul 01 06:12:52 PM PDT 24 |
37957003783 ps |
| T863 |
/workspace/coverage/default/4.sram_ctrl_executable.743759949 |
|
|
Jul 01 05:40:15 PM PDT 24 |
Jul 01 05:47:51 PM PDT 24 |
90066292617 ps |
| T864 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1027155925 |
|
|
Jul 01 05:43:09 PM PDT 24 |
Jul 01 05:43:11 PM PDT 24 |
16866995 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_alert_test.375779514 |
|
|
Jul 01 05:40:16 PM PDT 24 |
Jul 01 05:40:26 PM PDT 24 |
15785560 ps |
| T866 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1701486262 |
|
|
Jul 01 05:41:50 PM PDT 24 |
Jul 01 05:42:06 PM PDT 24 |
315754982 ps |
| T867 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1371523795 |
|
|
Jul 01 05:41:28 PM PDT 24 |
Jul 01 05:41:33 PM PDT 24 |
1354409313 ps |
| T868 |
/workspace/coverage/default/10.sram_ctrl_executable.585999053 |
|
|
Jul 01 05:40:36 PM PDT 24 |
Jul 01 05:51:50 PM PDT 24 |
12536641710 ps |
| T96 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.464696740 |
|
|
Jul 01 05:42:50 PM PDT 24 |
Jul 01 05:44:15 PM PDT 24 |
2760693259 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_smoke.572997908 |
|
|
Jul 01 05:40:41 PM PDT 24 |
Jul 01 05:42:24 PM PDT 24 |
1806901653 ps |
| T870 |
/workspace/coverage/default/34.sram_ctrl_bijection.167589760 |
|
|
Jul 01 05:44:17 PM PDT 24 |
Jul 01 06:02:52 PM PDT 24 |
692941773170 ps |
| T871 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2153395095 |
|
|
Jul 01 05:45:49 PM PDT 24 |
Jul 01 05:46:04 PM PDT 24 |
827881008 ps |
| T872 |
/workspace/coverage/default/42.sram_ctrl_regwen.1000396474 |
|
|
Jul 01 05:45:54 PM PDT 24 |
Jul 01 05:55:49 PM PDT 24 |
17692039672 ps |
| T873 |
/workspace/coverage/default/47.sram_ctrl_alert_test.408566048 |
|
|
Jul 01 05:46:54 PM PDT 24 |
Jul 01 05:46:55 PM PDT 24 |
15166795 ps |
| T874 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.4043924448 |
|
|
Jul 01 05:45:45 PM PDT 24 |
Jul 01 05:53:31 PM PDT 24 |
24214837922 ps |
| T875 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4187090323 |
|
|
Jul 01 05:42:44 PM PDT 24 |
Jul 01 06:02:08 PM PDT 24 |
140086191539 ps |
| T876 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1757688730 |
|
|
Jul 01 05:42:32 PM PDT 24 |
Jul 01 07:22:11 PM PDT 24 |
260724899675 ps |
| T877 |
/workspace/coverage/default/25.sram_ctrl_executable.103797976 |
|
|
Jul 01 05:42:43 PM PDT 24 |
Jul 01 05:56:31 PM PDT 24 |
27496107336 ps |
| T878 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.989825540 |
|
|
Jul 01 05:46:19 PM PDT 24 |
Jul 01 05:46:43 PM PDT 24 |
1355864890 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2270675639 |
|
|
Jul 01 05:44:43 PM PDT 24 |
Jul 01 05:49:25 PM PDT 24 |
9110863168 ps |
| T880 |
/workspace/coverage/default/8.sram_ctrl_bijection.2071401640 |
|
|
Jul 01 05:40:32 PM PDT 24 |
Jul 01 06:09:46 PM PDT 24 |
276720300923 ps |
| T881 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1110310210 |
|
|
Jul 01 05:40:29 PM PDT 24 |
Jul 01 05:42:09 PM PDT 24 |
15786679097 ps |
| T882 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1726815295 |
|
|
Jul 01 05:45:56 PM PDT 24 |
Jul 01 05:46:00 PM PDT 24 |
686163246 ps |
| T883 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2929574983 |
|
|
Jul 01 05:45:24 PM PDT 24 |
Jul 01 05:46:43 PM PDT 24 |
766988654 ps |
| T884 |
/workspace/coverage/default/34.sram_ctrl_regwen.945099959 |
|
|
Jul 01 05:44:22 PM PDT 24 |
Jul 01 06:03:48 PM PDT 24 |
40535869312 ps |
| T885 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1551328042 |
|
|
Jul 01 05:46:38 PM PDT 24 |
Jul 01 05:49:33 PM PDT 24 |
4894257095 ps |
| T886 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3502152891 |
|
|
Jul 01 05:42:31 PM PDT 24 |
Jul 01 05:45:15 PM PDT 24 |
9259879894 ps |
| T887 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2493793024 |
|
|
Jul 01 05:42:59 PM PDT 24 |
Jul 01 05:48:34 PM PDT 24 |
21118177962 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3014060893 |
|
|
Jul 01 05:41:59 PM PDT 24 |
Jul 01 05:43:18 PM PDT 24 |
2777340541 ps |
| T889 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1034010523 |
|
|
Jul 01 05:44:57 PM PDT 24 |
Jul 01 05:49:22 PM PDT 24 |
15209141934 ps |
| T890 |
/workspace/coverage/default/19.sram_ctrl_executable.220343170 |
|
|
Jul 01 05:41:36 PM PDT 24 |
Jul 01 05:59:36 PM PDT 24 |
10405720515 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1000689178 |
|
|
Jul 01 05:40:00 PM PDT 24 |
Jul 01 05:45:27 PM PDT 24 |
6015878716 ps |
| T892 |
/workspace/coverage/default/27.sram_ctrl_smoke.496168692 |
|
|
Jul 01 05:42:51 PM PDT 24 |
Jul 01 05:43:21 PM PDT 24 |
6917748059 ps |
| T893 |
/workspace/coverage/default/40.sram_ctrl_bijection.878030385 |
|
|
Jul 01 05:45:38 PM PDT 24 |
Jul 01 06:20:53 PM PDT 24 |
29037473758 ps |
| T894 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2535841001 |
|
|
Jul 01 05:45:00 PM PDT 24 |
Jul 01 06:00:21 PM PDT 24 |
11660799652 ps |
| T895 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2778770707 |
|
|
Jul 01 05:42:31 PM PDT 24 |
Jul 01 05:42:43 PM PDT 24 |
2641910264 ps |
| T896 |
/workspace/coverage/default/41.sram_ctrl_executable.2907546814 |
|
|
Jul 01 05:45:44 PM PDT 24 |
Jul 01 06:00:23 PM PDT 24 |
8952023021 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.593388890 |
|
|
Jul 01 05:40:50 PM PDT 24 |
Jul 01 05:44:33 PM PDT 24 |
14187291574 ps |
| T898 |
/workspace/coverage/default/32.sram_ctrl_regwen.906569297 |
|
|
Jul 01 05:44:08 PM PDT 24 |
Jul 01 05:57:01 PM PDT 24 |
14670889019 ps |
| T899 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1354904278 |
|
|
Jul 01 05:44:23 PM PDT 24 |
Jul 01 05:44:28 PM PDT 24 |
346041119 ps |
| T900 |
/workspace/coverage/default/29.sram_ctrl_regwen.2474919726 |
|
|
Jul 01 05:43:37 PM PDT 24 |
Jul 01 06:01:21 PM PDT 24 |
43200163889 ps |
| T901 |
/workspace/coverage/default/44.sram_ctrl_partial_access.903966013 |
|
|
Jul 01 05:46:07 PM PDT 24 |
Jul 01 05:48:55 PM PDT 24 |
2172433104 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_stress_all.730528255 |
|
|
Jul 01 05:42:16 PM PDT 24 |
Jul 01 06:09:35 PM PDT 24 |
100014204395 ps |
| T903 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2921417497 |
|
|
Jul 01 05:46:15 PM PDT 24 |
Jul 01 05:46:25 PM PDT 24 |
711134259 ps |
| T904 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3014341335 |
|
|
Jul 01 05:42:17 PM PDT 24 |
Jul 01 05:44:17 PM PDT 24 |
1971661520 ps |
| T905 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1410842826 |
|
|
Jul 01 05:42:03 PM PDT 24 |
Jul 01 05:44:39 PM PDT 24 |
1666159431 ps |
| T906 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3226659051 |
|
|
Jul 01 05:47:07 PM PDT 24 |
Jul 01 05:49:23 PM PDT 24 |
5816901348 ps |
| T907 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3164882594 |
|
|
Jul 01 05:41:43 PM PDT 24 |
Jul 01 05:50:13 PM PDT 24 |
13110971670 ps |
| T908 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2251154870 |
|
|
Jul 01 05:43:53 PM PDT 24 |
Jul 01 06:05:30 PM PDT 24 |
207047399601 ps |
| T909 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1277594894 |
|
|
Jul 01 05:44:44 PM PDT 24 |
Jul 01 05:52:31 PM PDT 24 |
10005588392 ps |
| T910 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2980529542 |
|
|
Jul 01 05:46:18 PM PDT 24 |
Jul 01 05:48:47 PM PDT 24 |
15190805000 ps |
| T911 |
/workspace/coverage/default/3.sram_ctrl_regwen.4271783444 |
|
|
Jul 01 05:40:13 PM PDT 24 |
Jul 01 06:10:59 PM PDT 24 |
18523171761 ps |
| T912 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1370355254 |
|
|
Jul 01 05:41:59 PM PDT 24 |
Jul 01 07:07:03 PM PDT 24 |
1232849777428 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4272231497 |
|
|
Jul 01 05:43:17 PM PDT 24 |
Jul 01 05:45:28 PM PDT 24 |
1612597624 ps |
| T33 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2656675385 |
|
|
Jul 01 05:40:06 PM PDT 24 |
Jul 01 05:40:12 PM PDT 24 |
380682437 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2182624664 |
|
|
Jul 01 05:40:51 PM PDT 24 |
Jul 01 05:54:08 PM PDT 24 |
29002555174 ps |
| T915 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3003996498 |
|
|
Jul 01 05:40:21 PM PDT 24 |
Jul 01 05:40:43 PM PDT 24 |
1051997081 ps |
| T916 |
/workspace/coverage/default/1.sram_ctrl_partial_access.964525562 |
|
|
Jul 01 05:40:05 PM PDT 24 |
Jul 01 05:41:48 PM PDT 24 |
2091725690 ps |
| T917 |
/workspace/coverage/default/28.sram_ctrl_bijection.2537518409 |
|
|
Jul 01 05:43:11 PM PDT 24 |
Jul 01 06:12:16 PM PDT 24 |
92037502451 ps |
| T918 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1676636370 |
|
|
Jul 01 05:41:59 PM PDT 24 |
Jul 01 05:52:11 PM PDT 24 |
20606411790 ps |
| T919 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1941872673 |
|
|
Jul 01 05:43:34 PM PDT 24 |
Jul 01 05:45:15 PM PDT 24 |
10231946959 ps |
| T920 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1809571658 |
|
|
Jul 01 05:46:44 PM PDT 24 |
Jul 01 05:56:34 PM PDT 24 |
22346705408 ps |
| T921 |
/workspace/coverage/default/40.sram_ctrl_regwen.2067935464 |
|
|
Jul 01 05:45:38 PM PDT 24 |
Jul 01 05:52:45 PM PDT 24 |
5426996018 ps |
| T922 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3627522555 |
|
|
Jul 01 05:40:20 PM PDT 24 |
Jul 01 06:05:11 PM PDT 24 |
75596150602 ps |
| T923 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1346000855 |
|
|
Jul 01 05:43:47 PM PDT 24 |
Jul 01 05:45:22 PM PDT 24 |
11116116879 ps |
| T924 |
/workspace/coverage/default/26.sram_ctrl_smoke.1161658518 |
|
|
Jul 01 05:42:45 PM PDT 24 |
Jul 01 05:42:59 PM PDT 24 |
3202357940 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.228096178 |
|
|
Jul 01 05:41:10 PM PDT 24 |
Jul 01 05:47:00 PM PDT 24 |
28138786434 ps |
| T926 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1362351570 |
|
|
Jul 01 05:40:06 PM PDT 24 |
Jul 01 05:40:11 PM PDT 24 |
36145552 ps |
| T927 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2861119477 |
|
|
Jul 01 05:46:19 PM PDT 24 |
Jul 01 05:54:07 PM PDT 24 |
28338288074 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_partial_access.755476535 |
|
|
Jul 01 05:41:08 PM PDT 24 |
Jul 01 05:41:32 PM PDT 24 |
5093632342 ps |
| T929 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1910900370 |
|
|
Jul 01 05:44:44 PM PDT 24 |
Jul 01 05:46:42 PM PDT 24 |
3074920888 ps |
| T930 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2144152223 |
|
|
Jul 01 05:44:17 PM PDT 24 |
Jul 01 05:45:00 PM PDT 24 |
1861269242 ps |
| T931 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3556385208 |
|
|
Jul 01 05:42:49 PM PDT 24 |
Jul 01 05:42:53 PM PDT 24 |
360523218 ps |
| T932 |
/workspace/coverage/default/44.sram_ctrl_executable.2905729721 |
|
|
Jul 01 05:46:17 PM PDT 24 |
Jul 01 06:09:15 PM PDT 24 |
5674964710 ps |
| T933 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1701230463 |
|
|
Jul 01 05:44:01 PM PDT 24 |
Jul 01 05:46:07 PM PDT 24 |
1306490239 ps |
| T934 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3304404745 |
|
|
Jul 01 05:40:04 PM PDT 24 |
Jul 01 06:10:28 PM PDT 24 |
82826969563 ps |
| T935 |
/workspace/coverage/default/45.sram_ctrl_smoke.1656149343 |
|
|
Jul 01 05:46:19 PM PDT 24 |
Jul 01 05:46:38 PM PDT 24 |
3690567373 ps |
| T936 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3679880922 |
|
|
Jul 01 05:42:43 PM PDT 24 |
Jul 01 05:50:29 PM PDT 24 |
5347466038 ps |
| T937 |
/workspace/coverage/default/6.sram_ctrl_executable.1453375767 |
|
|
Jul 01 05:40:18 PM PDT 24 |
Jul 01 06:02:59 PM PDT 24 |
47733762145 ps |
| T938 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3787342915 |
|
|
Jul 01 05:40:55 PM PDT 24 |
Jul 01 05:41:05 PM PDT 24 |
68558833 ps |
| T939 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1060615969 |
|
|
Jul 01 05:41:21 PM PDT 24 |
Jul 01 05:43:01 PM PDT 24 |
5324425208 ps |
| T940 |
/workspace/coverage/default/12.sram_ctrl_executable.1839715427 |
|
|
Jul 01 05:40:40 PM PDT 24 |
Jul 01 06:09:57 PM PDT 24 |
10866969745 ps |
| T941 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.683989858 |
|
|
Jul 01 05:40:07 PM PDT 24 |
Jul 01 05:40:47 PM PDT 24 |
26609204406 ps |
| T942 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.267941209 |
|
|
Jul 01 05:42:54 PM PDT 24 |
Jul 01 05:50:37 PM PDT 24 |
17181894129 ps |
| T943 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.153189211 |
|
|
Jul 01 05:44:25 PM PDT 24 |
Jul 01 05:49:54 PM PDT 24 |
27682619644 ps |
| T944 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3088442660 |
|
|
Jul 01 05:41:43 PM PDT 24 |
Jul 01 05:42:14 PM PDT 24 |
6685514390 ps |
| T945 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1852930562 |
|
|
Jul 01 05:45:27 PM PDT 24 |
Jul 01 05:46:21 PM PDT 24 |
9543881878 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2447967856 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:37 PM PDT 24 |
15650196 ps |
| T946 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3979477199 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:56 PM PDT 24 |
344711864 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.465566424 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:56 PM PDT 24 |
162218030 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1873356578 |
|
|
Jul 01 04:39:45 PM PDT 24 |
Jul 01 04:39:47 PM PDT 24 |
45448475 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1173974651 |
|
|
Jul 01 04:40:01 PM PDT 24 |
Jul 01 04:40:04 PM PDT 24 |
19282398 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2859564943 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
40850629 ps |
| T63 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2898585191 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:08 PM PDT 24 |
226810768 ps |
| T102 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.505710586 |
|
|
Jul 01 04:40:10 PM PDT 24 |
Jul 01 04:40:14 PM PDT 24 |
21377178 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2258409317 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:40 PM PDT 24 |
360281329 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.799428389 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:32 PM PDT 24 |
28998668 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2651526130 |
|
|
Jul 01 04:39:33 PM PDT 24 |
Jul 01 04:39:35 PM PDT 24 |
16471475 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2515842395 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:31 PM PDT 24 |
13462280 ps |
| T111 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.957212241 |
|
|
Jul 01 04:39:30 PM PDT 24 |
Jul 01 04:39:33 PM PDT 24 |
117309027 ps |
| T64 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.483126555 |
|
|
Jul 01 04:39:50 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
737603592 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.297306510 |
|
|
Jul 01 04:39:36 PM PDT 24 |
Jul 01 04:39:42 PM PDT 24 |
37993140 ps |
| T80 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2440497810 |
|
|
Jul 01 04:39:43 PM PDT 24 |
Jul 01 04:39:46 PM PDT 24 |
73276022 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2233230774 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:34 PM PDT 24 |
382385065 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1999413357 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:39:58 PM PDT 24 |
11805400 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1329261196 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:40:02 PM PDT 24 |
1179886964 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2284633783 |
|
|
Jul 01 04:39:31 PM PDT 24 |
Jul 01 04:39:34 PM PDT 24 |
88713147 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.402939412 |
|
|
Jul 01 04:39:57 PM PDT 24 |
Jul 01 04:40:28 PM PDT 24 |
3883605048 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3798743394 |
|
|
Jul 01 04:39:39 PM PDT 24 |
Jul 01 04:39:41 PM PDT 24 |
70631515 ps |
| T118 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3155304733 |
|
|
Jul 01 04:39:57 PM PDT 24 |
Jul 01 04:40:01 PM PDT 24 |
656007885 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2421856422 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:40:03 PM PDT 24 |
7403778221 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2493777321 |
|
|
Jul 01 04:40:08 PM PDT 24 |
Jul 01 04:40:11 PM PDT 24 |
143241961 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1740084521 |
|
|
Jul 01 04:39:35 PM PDT 24 |
Jul 01 04:39:40 PM PDT 24 |
130081995 ps |
| T953 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2940894244 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:40:02 PM PDT 24 |
711139105 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.469949737 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:37 PM PDT 24 |
451828215 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3050195732 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:36 PM PDT 24 |
35594055 ps |
| T120 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.953784530 |
|
|
Jul 01 04:39:30 PM PDT 24 |
Jul 01 04:39:33 PM PDT 24 |
261910858 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.381903825 |
|
|
Jul 01 04:39:58 PM PDT 24 |
Jul 01 04:40:02 PM PDT 24 |
237208659 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1823581550 |
|
|
Jul 01 04:39:40 PM PDT 24 |
Jul 01 04:40:08 PM PDT 24 |
21832257548 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.86002577 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:40:01 PM PDT 24 |
148066816 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.548563113 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
24271746 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4212290371 |
|
|
Jul 01 04:39:41 PM PDT 24 |
Jul 01 04:39:45 PM PDT 24 |
220595971 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.239125189 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:11 PM PDT 24 |
1913441132 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4005518031 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:53 PM PDT 24 |
12899207 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3234897743 |
|
|
Jul 01 04:39:50 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
362712698 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1275557659 |
|
|
Jul 01 04:39:28 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
41068467248 ps |
| T958 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4085224562 |
|
|
Jul 01 04:39:54 PM PDT 24 |
Jul 01 04:39:57 PM PDT 24 |
75715835 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2861893244 |
|
|
Jul 01 04:39:55 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
58808945 ps |
| T122 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.162432236 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:09 PM PDT 24 |
267508083 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1061171051 |
|
|
Jul 01 04:39:36 PM PDT 24 |
Jul 01 04:39:39 PM PDT 24 |
15430367 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1355624041 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:11 PM PDT 24 |
1422047744 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2772625531 |
|
|
Jul 01 04:39:43 PM PDT 24 |
Jul 01 04:39:49 PM PDT 24 |
1456445381 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3451517778 |
|
|
Jul 01 04:39:53 PM PDT 24 |
Jul 01 04:39:58 PM PDT 24 |
1459358244 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2572580397 |
|
|
Jul 01 04:39:52 PM PDT 24 |
Jul 01 04:39:55 PM PDT 24 |
42034755 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.403975398 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:55 PM PDT 24 |
124694576 ps |
| T90 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1376535322 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
69948993 ps |
| T965 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1034607715 |
|
|
Jul 01 04:40:00 PM PDT 24 |
Jul 01 04:40:05 PM PDT 24 |
354314486 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4126490494 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:32 PM PDT 24 |
266939394 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1730183117 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
182075065 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2078066533 |
|
|
Jul 01 04:39:43 PM PDT 24 |
Jul 01 04:39:48 PM PDT 24 |
318471470 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.885538984 |
|
|
Jul 01 04:39:48 PM PDT 24 |
Jul 01 04:39:52 PM PDT 24 |
349347867 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.773558112 |
|
|
Jul 01 04:39:35 PM PDT 24 |
Jul 01 04:39:38 PM PDT 24 |
40605100 ps |
| T971 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2299301304 |
|
|
Jul 01 04:40:05 PM PDT 24 |
Jul 01 04:40:07 PM PDT 24 |
11382759 ps |
| T972 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.621408001 |
|
|
Jul 01 04:39:43 PM PDT 24 |
Jul 01 04:39:46 PM PDT 24 |
27347201 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.396498803 |
|
|
Jul 01 04:39:35 PM PDT 24 |
Jul 01 04:39:42 PM PDT 24 |
361035577 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2479346303 |
|
|
Jul 01 04:39:28 PM PDT 24 |
Jul 01 04:39:58 PM PDT 24 |
7553773269 ps |
| T974 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.37935215 |
|
|
Jul 01 04:39:59 PM PDT 24 |
Jul 01 04:40:05 PM PDT 24 |
140604136 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1184323357 |
|
|
Jul 01 04:39:30 PM PDT 24 |
Jul 01 04:39:32 PM PDT 24 |
18863193 ps |
| T976 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1338932203 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:36 PM PDT 24 |
28494351341 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.604417437 |
|
|
Jul 01 04:40:03 PM PDT 24 |
Jul 01 04:40:08 PM PDT 24 |
180244004 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1317041350 |
|
|
Jul 01 04:39:32 PM PDT 24 |
Jul 01 04:39:35 PM PDT 24 |
124804389 ps |
| T97 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1914328839 |
|
|
Jul 01 04:39:46 PM PDT 24 |
Jul 01 04:40:40 PM PDT 24 |
7407165839 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2197181363 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:38 PM PDT 24 |
239574669 ps |
| T98 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1207706027 |
|
|
Jul 01 04:39:35 PM PDT 24 |
Jul 01 04:39:38 PM PDT 24 |
23097278 ps |
| T980 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.11564366 |
|
|
Jul 01 04:39:49 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
105412522 ps |
| T123 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4014508125 |
|
|
Jul 01 04:39:55 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
495462133 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2490397853 |
|
|
Jul 01 04:39:57 PM PDT 24 |
Jul 01 04:40:04 PM PDT 24 |
1488933809 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1445794023 |
|
|
Jul 01 04:40:02 PM PDT 24 |
Jul 01 04:40:04 PM PDT 24 |
39548268 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1019428137 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:40:56 PM PDT 24 |
41376734908 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3397972298 |
|
|
Jul 01 04:39:27 PM PDT 24 |
Jul 01 04:39:28 PM PDT 24 |
63392024 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.506998426 |
|
|
Jul 01 04:39:42 PM PDT 24 |
Jul 01 04:39:49 PM PDT 24 |
132489666 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4233731528 |
|
|
Jul 01 04:39:45 PM PDT 24 |
Jul 01 04:39:50 PM PDT 24 |
1432577648 ps |
| T986 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4049461364 |
|
|
Jul 01 04:39:53 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
1327934458 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.619717898 |
|
|
Jul 01 04:39:35 PM PDT 24 |
Jul 01 04:39:39 PM PDT 24 |
698079864 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1644253740 |
|
|
Jul 01 04:39:31 PM PDT 24 |
Jul 01 04:39:33 PM PDT 24 |
19969626 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3230956415 |
|
|
Jul 01 04:39:39 PM PDT 24 |
Jul 01 04:39:41 PM PDT 24 |
37310723 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1390550663 |
|
|
Jul 01 04:39:45 PM PDT 24 |
Jul 01 04:39:50 PM PDT 24 |
720835085 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.830603409 |
|
|
Jul 01 04:39:57 PM PDT 24 |
Jul 01 04:40:51 PM PDT 24 |
9824020691 ps |
| T125 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4261561344 |
|
|
Jul 01 04:39:59 PM PDT 24 |
Jul 01 04:40:03 PM PDT 24 |
527766445 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1445855761 |
|
|
Jul 01 04:39:28 PM PDT 24 |
Jul 01 04:39:34 PM PDT 24 |
369633432 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1939037520 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:35 PM PDT 24 |
622217741 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2360963866 |
|
|
Jul 01 04:40:06 PM PDT 24 |
Jul 01 04:40:08 PM PDT 24 |
15679910 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1803569669 |
|
|
Jul 01 04:39:30 PM PDT 24 |
Jul 01 04:39:33 PM PDT 24 |
146426933 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1096221014 |
|
|
Jul 01 04:39:34 PM PDT 24 |
Jul 01 04:39:39 PM PDT 24 |
353791662 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1952535495 |
|
|
Jul 01 04:39:36 PM PDT 24 |
Jul 01 04:40:39 PM PDT 24 |
29414206700 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.588079976 |
|
|
Jul 01 04:39:28 PM PDT 24 |
Jul 01 04:39:35 PM PDT 24 |
148748956 ps |
| T129 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2909085873 |
|
|
Jul 01 04:39:40 PM PDT 24 |
Jul 01 04:39:43 PM PDT 24 |
120363010 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2059413667 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:40:28 PM PDT 24 |
36965805395 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2746968470 |
|
|
Jul 01 04:39:29 PM PDT 24 |
Jul 01 04:39:31 PM PDT 24 |
24424667 ps |
| T999 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.763175244 |
|
|
Jul 01 04:39:51 PM PDT 24 |
Jul 01 04:39:54 PM PDT 24 |
17102273 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3695566686 |
|
|
Jul 01 04:39:49 PM PDT 24 |
Jul 01 04:39:51 PM PDT 24 |
27444465 ps |
| T1001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3497887054 |
|
|
Jul 01 04:40:01 PM PDT 24 |
Jul 01 04:40:06 PM PDT 24 |
430921530 ps |
| T1002 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3678542009 |
|
|
Jul 01 04:39:42 PM PDT 24 |
Jul 01 04:39:44 PM PDT 24 |
24109801 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2364787601 |
|
|
Jul 01 04:39:58 PM PDT 24 |
Jul 01 04:40:04 PM PDT 24 |
67232368 ps |
| T1004 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1692154442 |
|
|
Jul 01 04:39:53 PM PDT 24 |
Jul 01 04:39:56 PM PDT 24 |
44982915 ps |
| T1005 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3009912851 |
|
|
Jul 01 04:39:56 PM PDT 24 |
Jul 01 04:39:59 PM PDT 24 |
28211185 ps |