SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 348756364 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
instr_valid_dis | 306258711 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
instr_en | 31341927 | 1 | T26 | 173368 | T7 | 20000 | T28 | 331980 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 13611158 | 1 | T26 | 35146 | T7 | 181572 | T28 | 33566 | ||||
sram_ifetch_valid_disable | 307395064 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
sram_ifetch_enable | 27750142 | 1 | T26 | 153368 | T7 | 189864 | T28 | 183700 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 348756364 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
hw_debug_en_valid_off | 307846215 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
hw_debug_en_on | 28643360 | 1 | T26 | 131414 | T7 | 310162 | T28 | 68118 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 307395064 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 286259753 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 14321055 | 1 | T26 | 20000 | T7 | 20000 | T28 | 114714 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 6773050 | 1 | T26 | 23242 | T7 | 111946 | T28 | 11612 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 4413860 | 1 | T26 | 23242 | T7 | 110196 | T127 | 20398 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 1805124 | 1 | T28 | 11612 | T23 | 126700 | T128 | 14440 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 4855228 | 1 | T26 | 11904 | T7 | 69626 | T28 | 266 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 2285180 | 1 | T7 | 69626 | T129 | 45830 | T24 | 8722 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 2086082 | 1 | T28 | 266 | T127 | 27330 | T130 | 28358 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 12174894 | 1 | T26 | 35128 | T7 | 115708 | T28 | 52888 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 4885034 | 1 | T26 | 35128 | T7 | 95708 | T36 | 74068 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 6306622 | 1 | T7 | 20000 | T28 | 52888 | T23 | 54442 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 12268830 | 1 | T26 | 153368 | T28 | 183700 | T23 | 110814 | ||||
lc_exec_en | 11613238 | 1 | T26 | 84382 | T7 | 124828 | T28 | 14964 | ||||
valid_exec_dis | 303254885 | 1 | T1 | 300510 | T3 | 12650 | T4 | 5070 | ||||
invalid_exec_dis | 41361300 | 1 | T26 | 188514 | T7 | 371436 | T28 | 217266 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |