Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	143738965	1			T1	136751		T3	5755		T11	137625
triple_byte_access	2786801	1			T1	2633		T3	117		T13	6821
halfword_access	4284384	1			T1	4118		T3	163		T13	12601
byte_access	5998853	1			T1	5399		T3	232		T13	24084
zero_access	1830093	1			T1	1354		T3	58		T13	14241

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79100526

1

T1

75308

T3

3189

T11

688128

auto[1]

79538570

1

T1

74947

T3

3136

T11

688128

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71501889	1			T1	68613		T3	2913		T11	688128
auto[0]	triple_byte_access	1326818	1			T1	1308		T3	62		T13	1274
auto[0]	halfword_access	2092943	1			T1	2053		T3	71		T13	4367
auto[0]	byte_access	3078494	1			T1	2691		T3	114		T13	12997
auto[0]	zero_access	1100382	1			T1	643		T3	29		T13	11510
auto[1]	word_access	72237076	1			T1	68138		T3	2842		T11	688128
auto[1]	triple_byte_access	1459983	1			T1	1325		T3	55		T13	5547
auto[1]	halfword_access	2191441	1			T1	2065		T3	92		T13	8234
auto[1]	byte_access	2920359	1			T1	2708		T3	118		T13	11087
auto[1]	zero_access	729711	1			T1	711		T3	29		T13	2731