Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	352675618	1			T1	156468		T2	3502		T3	18352
instr_valid_dis	313853841	1			T1	156468		T2	3502		T3	18352
instr_en	28198601	1			T10	143028		T7	350212		T27	109302

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10924749	1			T10	73518		T7	73394		T27	53220
sram_ifetch_valid_disable	309729267	1			T1	156468		T2	3502		T3	18352
sram_ifetch_enable	32021602	1			T10	101038		T7	155320		T27	191576

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	352675618	1			T1	156468		T2	3502		T3	18352
hw_debug_en_valid_off	309999706	1			T1	156468		T2	3502		T3	18352
hw_debug_en_on	29617444	1			T10	214786		T7	105634		T27	255834

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	309729267	1			T1	156468		T2	3502		T3	18352
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	295738290	1			T1	156468		T2	3502		T3	18352
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10774371	1			T10	83960		T7	121608		T27	91734
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4465801	1			T10	54450		T7	11516		T27	42312
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2162939	1			T10	14450		T27	42312		T20	6216
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1860712	1			T10	40000		T7	11516		T21	59560
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4232602	1			T10	19068		T7	43340		T27	10908
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1609656	1			T27	10908		T20	12070		T21	14566
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2110858	1			T10	19068		T7	43340		T20	24612
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	16421394	1			T10	94680		T7	38348		T27	164310
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	10042728	1			T10	22660		T27	129510		T20	56160
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5236826	1			T10	72020		T7	26218		T27	34800

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12508092	1			T7	155210		T27	17568		T104	24630
lc_exec_en	8963448	1			T10	101038		T7	23946		T27	80616
valid_exec_dis	302926177	1			T1	156468		T2	3502		T3	18352
invalid_exec_dis	42946351	1			T10	174556		T7	228714		T27	244796