Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	146883561	1			T1	71087		T2	456		T3	9176
triple_byte_access	2882775	1			T1	1476		T2	12		T4	385
halfword_access	4424942	1			T1	2145		T2	12		T4	503
byte_access	6189493	1			T1	2856		T2	17		T4	737
zero_access	1873798	1			T1	670		T2	4		T4	182

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80969996

1

T1

38867

T2

270

T3

4552

auto[1]

81284573

1

T1

39367

T2

231

T3

4624

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	73138081	1			T1	35322		T2	250		T3	4552
auto[0]	triple_byte_access	1375716	1			T1	750		T2	4		T4	189
auto[0]	halfword_access	2163819	1			T1	1073		T2	7		T4	266
auto[0]	byte_access	3172195	1			T1	1375		T2	7		T4	372
auto[0]	zero_access	1120185	1			T1	347		T2	2		T4	94
auto[1]	word_access	73745480	1			T1	35765		T2	206		T3	4624
auto[1]	triple_byte_access	1507059	1			T1	726		T2	8		T4	196
auto[1]	halfword_access	2261123	1			T1	1072		T2	5		T4	237
auto[1]	byte_access	3017298	1			T1	1481		T2	10		T4	365
auto[1]	zero_access	753613	1			T1	323		T2	2		T4	88