Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	339350586	1			T1	62062		T2	460436		T3	121544
instr_valid_dis	298304490	1			T1	3454		T2	60		T3	121544
instr_en	27317473	1			T1	33920		T2	454462		T4	34286

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18624627	1			T2	127494		T4	15634		T19	331936
sram_ifetch_valid_disable	293790140	1			T1	39816		T2	34938		T3	121544
sram_ifetch_enable	26935819	1			T1	22246		T2	298004		T4	52970

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	339350586	1			T1	62062		T2	460436		T3	121544
hw_debug_en_valid_off	295420568	1			T1	43270		T2	262258		T3	121544
hw_debug_en_on	31489146	1			T1	18792		T2	128886		T4	28240

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	293790140	1			T1	39816		T2	34938		T3	121544
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	277616440	1			T2	60		T3	121544		T5	550772
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10610049	1			T1	15128		T2	34878		T19	265750
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	10150446	1			T2	69508		T19	328382		T8	36342
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4602352	1			T19	49268		T8	36342		T82	11096
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1724556	1			T2	69508		T19	16186		T20	84402
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4467216	1			T2	18276		T8	31770		T20	30632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1903318	1			T8	16108		T82	20000		T158	17800
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1966470	1			T2	18276		T8	15662		T20	30632
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13292516	1			T2	60		T4	642		T19	223892
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4101804	1			T2	60		T4	642		T19	63244
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5353448	1			T19	136048		T77	41590		T8	45262

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12221952	1			T1	18792		T2	292090		T4	34286
lc_exec_en	13729414	1			T1	18792		T2	110550		T4	27598
valid_exec_dis	287684661	1			T1	43270		T2	19932		T3	121544
invalid_exec_dis	45560446	1			T1	22246		T2	425498		T4	68604