Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140116188	1			T1	13076		T2	112107		T3	3048
triple_byte_access	2785123	1			T1	248		T2	2184		T3	6900
halfword_access	4271138	1			T1	403		T2	3461		T3	12532
byte_access	5969712	1			T1	480		T2	4313		T3	24195
zero_access	1802675	1			T1	126		T2	1124		T3	14097

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77306567

1

T1

8080

T2

76974

T3

30208

auto[1]

77638269

1

T1

6253

T2

46215

T3

30564

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69741953	1			T1	7388		T2	69977		T3	260
auto[0]	triple_byte_access	1331849	1			T1	135		T2	1399		T3	1356
auto[0]	halfword_access	2093763	1			T1	213		T2	2187		T3	4362
auto[0]	byte_access	3062161	1			T1	273		T2	2696		T3	12982
auto[0]	zero_access	1076841	1			T1	71		T2	715		T3	11248
auto[1]	word_access	70374235	1			T1	5688		T2	42130		T3	2788
auto[1]	triple_byte_access	1453274	1			T1	113		T2	785		T3	5544
auto[1]	halfword_access	2177375	1			T1	190		T2	1274		T3	8170
auto[1]	byte_access	2907551	1			T1	207		T2	1617		T3	11213
auto[1]	zero_access	725834	1			T1	55		T2	409		T3	2849