Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	385094044	1			T1	23980		T3	17564		T4	7228
instr_valid_dis	345186628	1			T1	23980		T3	17564		T4	7228
instr_en	25076032	1			T22	128888		T24	160886		T19	365854

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15397384	1			T22	17578		T24	204298		T19	96594
sram_ifetch_valid_disable	340317660	1			T1	23980		T3	17564		T4	7228
sram_ifetch_enable	29379000	1			T22	193148		T24	284920		T19	124986

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	385094044	1			T1	23980		T3	17564		T4	7228
hw_debug_en_valid_off	344621167	1			T1	23980		T3	17564		T4	7228
hw_debug_en_on	29109257	1			T22	216026		T24	158742		T19	196824

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	340317660	1			T1	23980		T3	17564		T4	7228
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	326057526	1			T1	23980		T3	17564		T4	7228
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9583144	1			T22	62654		T24	25038		T19	144274
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4264762	1			T24	62418		T19	61304		T6	120608
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1844424	1			T24	44146		T6	89590		T119	60484
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1648948	1			T24	18272		T19	61304		T6	31018
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	8609006	1			T22	17578		T24	100372		T19	35290
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2097230	1			T22	17578		T7	49180		T119	37784
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1944092	1			T24	62000		T19	35290		T135	33144
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10207213	1			T22	83364		T24	2742		T19	76418
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4237392	1			T22	47304		T24	2742		T135	13830
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3966735	1			T22	36060		T19	76418		T135	32132

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10924188	1			T22	66234		T24	55576		T19	124986
lc_exec_en	10293038	1			T22	115084		T24	55628		T19	85116
valid_exec_dis	339808657	1			T1	23980		T3	17564		T4	7228
invalid_exec_dis	44776384	1			T22	210726		T24	489218		T19	221580