Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	161203558	1			T1	1022		T3	1566		T4	244
triple_byte_access	2857902	1			T1	22		T3	1410		T4	5
halfword_access	4381809	1			T1	28		T3	2215		T4	8
byte_access	6117077	1			T1	38		T3	2854		T4	10
zero_access	1842292	1			T1	6		T3	737		T5	18841

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88161313

1

T1

527

T3

4339

T4

138

auto[1]

88241325

1

T1

589

T3

4443

T4

129

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	80410515	1			T1	484		T3	770		T4	129
auto[0]	triple_byte_access	1368823	1			T1	11		T3	687		T4	2
auto[0]	halfword_access	2146259	1			T1	12		T3	1085		T4	3
auto[0]	byte_access	3138303	1			T1	19		T3	1419		T4	4
auto[0]	zero_access	1097413	1			T1	1		T3	378		T5	9398
auto[1]	word_access	80793043	1			T1	538		T3	796		T4	115
auto[1]	triple_byte_access	1489079	1			T1	11		T3	723		T4	3
auto[1]	halfword_access	2235550	1			T1	16		T3	1130		T4	5
auto[1]	byte_access	2978774	1			T1	19		T3	1435		T4	6
auto[1]	zero_access	744879	1			T1	5		T3	359		T5	9443