Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	388812538	1			T1	8802		T2	240962		T3	20000
instr_valid_dis	333965451	1			T1	8802		T2	122780		T3	20000
instr_en	29532437	1			T2	46280		T8	267650		T25	47070

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	20713530	1			T2	13978		T8	98020		T26	13344
sram_ifetch_valid_disable	335791837	1			T1	8802		T2	35136		T3	20000
sram_ifetch_enable	32307171	1			T2	191848		T8	48338		T25	24242

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	388812538	1			T1	8802		T2	240962		T3	20000
hw_debug_en_valid_off	338633267	1			T1	8802		T2	51630		T3	20000
hw_debug_en_on	31087984	1			T2	114070		T8	101186		T25	20000

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	335791837	1			T1	8802		T2	35136		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	315061053	1			T1	8802		T3	20000		T4	15504
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12808236	1			T2	35136		T8	121292		T25	47070
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	10281458	1			T2	13978		T8	67818		T26	13344
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1757512	1			T26	13344		T70	38524		T20	40820
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4335036	1			T8	67818		T133	1140		T21	33310
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4526018	1			T8	30202		T70	46870		T20	83140
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1806462	1			T70	46870		T20	83140		T21	43548
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1893672	1			T8	30202		T21	18632		T131	40862
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14742418	1			T2	17798		T8	29226		T25	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5894032	1			T70	73752		T20	92196		T21	141499
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3177780	1			T2	17798		T8	29226		T25	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8414229	1			T2	11144		T8	48338		T133	9490
lc_exec_en	11819548	1			T2	96272		T8	41758		T53	18174
valid_exec_dis	330209199	1			T1	8802		T2	122780		T3	20000
invalid_exec_dis	53020701	1			T2	205826		T8	146358		T25	24242