Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	164365204	1			T2	46686		T3	10000		T4	7057
triple_byte_access	2852851	1			T2	937		T4	139		T8	1156
halfword_access	4372680	1			T2	1351		T4	169		T8	1767
byte_access	6097844	1			T2	1846		T4	316		T8	2355
zero_access	1829803	1			T2	458		T4	71		T8	578

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89522100

1

T2

27082

T3

4950

T4

3761

auto[1]

89996282

1

T2

24196

T3

5050

T4

3991

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	81811879	1			T2	24637		T3	4950		T4	3425
auto[0]	triple_byte_access	1364547	1			T2	491		T4	72		T8	630
auto[0]	halfword_access	2140687	1			T2	740		T4	86		T8	1044
auto[0]	byte_access	3120145	1			T2	953		T4	143		T8	1369
auto[0]	zero_access	1084842	1			T2	261		T4	35		T8	348
auto[1]	word_access	82553325	1			T2	22049		T3	5050		T4	3632
auto[1]	triple_byte_access	1488304	1			T2	446		T4	67		T8	526
auto[1]	halfword_access	2231993	1			T2	611		T4	83		T8	723
auto[1]	byte_access	2977699	1			T2	893		T4	173		T8	986
auto[1]	zero_access	744961	1			T2	197		T4	36		T8	230