| T790 |
/workspace/coverage/default/17.sram_ctrl_smoke.2881630874 |
|
|
Jul 17 07:21:12 PM PDT 24 |
Jul 17 07:21:28 PM PDT 24 |
3642228023 ps |
| T791 |
/workspace/coverage/default/49.sram_ctrl_smoke.3713516111 |
|
|
Jul 17 07:26:33 PM PDT 24 |
Jul 17 07:26:42 PM PDT 24 |
879116964 ps |
| T792 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1565843781 |
|
|
Jul 17 07:26:33 PM PDT 24 |
Jul 17 07:26:37 PM PDT 24 |
1974814115 ps |
| T793 |
/workspace/coverage/default/6.sram_ctrl_executable.4183892782 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:43:14 PM PDT 24 |
21826866718 ps |
| T794 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3622533609 |
|
|
Jul 17 07:24:51 PM PDT 24 |
Jul 17 07:41:32 PM PDT 24 |
36566945699 ps |
| T795 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.224113238 |
|
|
Jul 17 07:24:18 PM PDT 24 |
Jul 17 07:32:30 PM PDT 24 |
17250372298 ps |
| T796 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3257837871 |
|
|
Jul 17 07:26:32 PM PDT 24 |
Jul 17 07:35:29 PM PDT 24 |
83993604269 ps |
| T797 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.955403504 |
|
|
Jul 17 07:24:12 PM PDT 24 |
Jul 17 07:25:12 PM PDT 24 |
8829434380 ps |
| T798 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2751622837 |
|
|
Jul 17 07:24:16 PM PDT 24 |
Jul 17 07:24:26 PM PDT 24 |
1200357249 ps |
| T799 |
/workspace/coverage/default/30.sram_ctrl_executable.1390338320 |
|
|
Jul 17 07:24:08 PM PDT 24 |
Jul 17 07:31:51 PM PDT 24 |
52726472177 ps |
| T800 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3533321748 |
|
|
Jul 17 07:21:02 PM PDT 24 |
Jul 17 07:21:35 PM PDT 24 |
3114420396 ps |
| T801 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3539706048 |
|
|
Jul 17 07:25:37 PM PDT 24 |
Jul 17 07:46:50 PM PDT 24 |
16189236200 ps |
| T802 |
/workspace/coverage/default/15.sram_ctrl_regwen.2661540198 |
|
|
Jul 17 07:21:12 PM PDT 24 |
Jul 17 07:42:00 PM PDT 24 |
17557852847 ps |
| T803 |
/workspace/coverage/default/40.sram_ctrl_regwen.317144983 |
|
|
Jul 17 07:24:56 PM PDT 24 |
Jul 17 07:30:16 PM PDT 24 |
1823577991 ps |
| T804 |
/workspace/coverage/default/40.sram_ctrl_bijection.3444442996 |
|
|
Jul 17 07:24:51 PM PDT 24 |
Jul 17 07:52:46 PM PDT 24 |
106776950093 ps |
| T805 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2518534535 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:23:04 PM PDT 24 |
6543689329 ps |
| T806 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2553299881 |
|
|
Jul 17 07:24:04 PM PDT 24 |
Jul 17 07:29:40 PM PDT 24 |
24405324470 ps |
| T807 |
/workspace/coverage/default/0.sram_ctrl_regwen.1960949863 |
|
|
Jul 17 07:20:43 PM PDT 24 |
Jul 17 07:30:58 PM PDT 24 |
5795169349 ps |
| T808 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1292038653 |
|
|
Jul 17 07:20:46 PM PDT 24 |
Jul 17 07:21:38 PM PDT 24 |
5955719648 ps |
| T809 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2973142020 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:22:33 PM PDT 24 |
2803406579 ps |
| T810 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3766277539 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:21:40 PM PDT 24 |
27586249527 ps |
| T811 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2350178519 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:40:33 PM PDT 24 |
52277279644 ps |
| T812 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1331015097 |
|
|
Jul 17 07:25:04 PM PDT 24 |
Jul 17 07:27:34 PM PDT 24 |
10406650909 ps |
| T813 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4185694068 |
|
|
Jul 17 07:25:34 PM PDT 24 |
Jul 17 07:28:16 PM PDT 24 |
787162055 ps |
| T814 |
/workspace/coverage/default/0.sram_ctrl_executable.2878271531 |
|
|
Jul 17 07:20:46 PM PDT 24 |
Jul 17 07:27:48 PM PDT 24 |
34243540214 ps |
| T815 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2519303153 |
|
|
Jul 17 07:25:36 PM PDT 24 |
Jul 17 07:26:31 PM PDT 24 |
9301553036 ps |
| T816 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3999944606 |
|
|
Jul 17 07:24:06 PM PDT 24 |
Jul 17 07:24:15 PM PDT 24 |
180833777 ps |
| T817 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3572384797 |
|
|
Jul 17 07:26:04 PM PDT 24 |
Jul 17 07:26:37 PM PDT 24 |
5828801942 ps |
| T818 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1014780264 |
|
|
Jul 17 07:21:13 PM PDT 24 |
Jul 17 07:21:27 PM PDT 24 |
1427568345 ps |
| T819 |
/workspace/coverage/default/49.sram_ctrl_partial_access.880119538 |
|
|
Jul 17 07:26:34 PM PDT 24 |
Jul 17 07:29:01 PM PDT 24 |
5622569748 ps |
| T820 |
/workspace/coverage/default/41.sram_ctrl_bijection.397651780 |
|
|
Jul 17 07:24:52 PM PDT 24 |
Jul 17 08:01:51 PM PDT 24 |
498486634033 ps |
| T821 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1631908005 |
|
|
Jul 17 07:21:16 PM PDT 24 |
Jul 17 07:22:17 PM PDT 24 |
773869566 ps |
| T822 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3742213436 |
|
|
Jul 17 07:26:01 PM PDT 24 |
Jul 17 08:36:18 PM PDT 24 |
203650741723 ps |
| T823 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.928459223 |
|
|
Jul 17 07:20:42 PM PDT 24 |
Jul 17 07:21:51 PM PDT 24 |
773776131 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3765549407 |
|
|
Jul 17 07:20:48 PM PDT 24 |
Jul 17 07:21:03 PM PDT 24 |
391648876 ps |
| T825 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.18828667 |
|
|
Jul 17 07:25:35 PM PDT 24 |
Jul 17 07:25:46 PM PDT 24 |
972551434 ps |
| T826 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3264905209 |
|
|
Jul 17 07:24:07 PM PDT 24 |
Jul 17 07:26:09 PM PDT 24 |
1658341061 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.196138899 |
|
|
Jul 17 07:24:56 PM PDT 24 |
Jul 17 07:25:00 PM PDT 24 |
2123784374 ps |
| T828 |
/workspace/coverage/default/36.sram_ctrl_alert_test.628857722 |
|
|
Jul 17 07:24:50 PM PDT 24 |
Jul 17 07:24:53 PM PDT 24 |
13254165 ps |
| T829 |
/workspace/coverage/default/28.sram_ctrl_partial_access.719408812 |
|
|
Jul 17 07:24:04 PM PDT 24 |
Jul 17 07:24:22 PM PDT 24 |
1133588223 ps |
| T830 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3200605436 |
|
|
Jul 17 07:24:16 PM PDT 24 |
Jul 17 07:30:34 PM PDT 24 |
35800522054 ps |
| T831 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1273796257 |
|
|
Jul 17 07:20:50 PM PDT 24 |
Jul 17 07:22:42 PM PDT 24 |
909920009 ps |
| T832 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1295149470 |
|
|
Jul 17 07:25:42 PM PDT 24 |
Jul 17 07:25:54 PM PDT 24 |
1991416669 ps |
| T833 |
/workspace/coverage/default/35.sram_ctrl_regwen.2565274213 |
|
|
Jul 17 07:24:10 PM PDT 24 |
Jul 17 07:50:03 PM PDT 24 |
23478569884 ps |
| T834 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3043262093 |
|
|
Jul 17 07:24:09 PM PDT 24 |
Jul 17 07:24:20 PM PDT 24 |
719206302 ps |
| T835 |
/workspace/coverage/default/13.sram_ctrl_smoke.412905047 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:21:12 PM PDT 24 |
776398434 ps |
| T836 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2343600497 |
|
|
Jul 17 07:26:35 PM PDT 24 |
Jul 17 07:27:55 PM PDT 24 |
14976304446 ps |
| T837 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3695515058 |
|
|
Jul 17 07:23:30 PM PDT 24 |
Jul 17 07:26:05 PM PDT 24 |
810827562 ps |
| T838 |
/workspace/coverage/default/26.sram_ctrl_smoke.2117431017 |
|
|
Jul 17 07:24:02 PM PDT 24 |
Jul 17 07:24:27 PM PDT 24 |
2182341180 ps |
| T839 |
/workspace/coverage/default/9.sram_ctrl_smoke.1595525144 |
|
|
Jul 17 07:20:44 PM PDT 24 |
Jul 17 07:22:55 PM PDT 24 |
1226935966 ps |
| T840 |
/workspace/coverage/default/25.sram_ctrl_bijection.1768906438 |
|
|
Jul 17 07:23:33 PM PDT 24 |
Jul 17 08:03:51 PM PDT 24 |
211024626701 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3656839704 |
|
|
Jul 17 07:25:07 PM PDT 24 |
Jul 17 07:26:07 PM PDT 24 |
746249152 ps |
| T842 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1004654290 |
|
|
Jul 17 07:24:09 PM PDT 24 |
Jul 17 07:24:22 PM PDT 24 |
4273372930 ps |
| T843 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.693755815 |
|
|
Jul 17 07:20:37 PM PDT 24 |
Jul 17 07:20:44 PM PDT 24 |
689718229 ps |
| T844 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3981708425 |
|
|
Jul 17 07:26:34 PM PDT 24 |
Jul 17 07:26:46 PM PDT 24 |
767121681 ps |
| T845 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2724793817 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:22:16 PM PDT 24 |
6069122376 ps |
| T846 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2870590109 |
|
|
Jul 17 07:25:39 PM PDT 24 |
Jul 17 07:30:44 PM PDT 24 |
21876907975 ps |
| T847 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2437078456 |
|
|
Jul 17 07:21:13 PM PDT 24 |
Jul 17 07:21:30 PM PDT 24 |
713841296 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1821289350 |
|
|
Jul 17 07:24:54 PM PDT 24 |
Jul 17 07:24:59 PM PDT 24 |
365870022 ps |
| T849 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4200623694 |
|
|
Jul 17 07:24:06 PM PDT 24 |
Jul 17 07:24:09 PM PDT 24 |
12180785 ps |
| T850 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3051266594 |
|
|
Jul 17 07:25:36 PM PDT 24 |
Jul 17 07:25:42 PM PDT 24 |
348295225 ps |
| T851 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3828244319 |
|
|
Jul 17 07:24:21 PM PDT 24 |
Jul 17 07:43:43 PM PDT 24 |
17479770444 ps |
| T852 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1744705243 |
|
|
Jul 17 07:23:31 PM PDT 24 |
Jul 17 09:22:21 PM PDT 24 |
278398594949 ps |
| T853 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1217091772 |
|
|
Jul 17 07:24:09 PM PDT 24 |
Jul 17 07:44:52 PM PDT 24 |
19132359676 ps |
| T854 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3039613491 |
|
|
Jul 17 07:20:57 PM PDT 24 |
Jul 17 07:24:09 PM PDT 24 |
148052309263 ps |
| T855 |
/workspace/coverage/default/19.sram_ctrl_smoke.3589642409 |
|
|
Jul 17 07:21:17 PM PDT 24 |
Jul 17 07:21:34 PM PDT 24 |
917970255 ps |
| T856 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2646495914 |
|
|
Jul 17 07:22:24 PM PDT 24 |
Jul 17 07:24:58 PM PDT 24 |
3906553459 ps |
| T857 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2004520786 |
|
|
Jul 17 07:20:46 PM PDT 24 |
Jul 17 07:25:25 PM PDT 24 |
18743801447 ps |
| T858 |
/workspace/coverage/default/27.sram_ctrl_regwen.2913633495 |
|
|
Jul 17 07:24:06 PM PDT 24 |
Jul 17 07:39:54 PM PDT 24 |
109085634261 ps |
| T859 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3203646369 |
|
|
Jul 17 07:24:08 PM PDT 24 |
Jul 17 07:26:52 PM PDT 24 |
1431983723 ps |
| T860 |
/workspace/coverage/default/29.sram_ctrl_regwen.3921170002 |
|
|
Jul 17 07:24:12 PM PDT 24 |
Jul 17 07:27:02 PM PDT 24 |
1712231739 ps |
| T861 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3267260135 |
|
|
Jul 17 07:24:11 PM PDT 24 |
Jul 17 07:33:00 PM PDT 24 |
313540882294 ps |
| T862 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.302100809 |
|
|
Jul 17 07:23:31 PM PDT 24 |
Jul 17 07:23:38 PM PDT 24 |
6664222294 ps |
| T863 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3171270516 |
|
|
Jul 17 07:22:25 PM PDT 24 |
Jul 17 07:23:03 PM PDT 24 |
737307069 ps |
| T864 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2797116266 |
|
|
Jul 17 07:22:22 PM PDT 24 |
Jul 17 07:29:55 PM PDT 24 |
22067619129 ps |
| T865 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3038715919 |
|
|
Jul 17 07:21:14 PM PDT 24 |
Jul 17 08:15:20 PM PDT 24 |
48323851957 ps |
| T866 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4020009242 |
|
|
Jul 17 07:20:48 PM PDT 24 |
Jul 17 07:21:27 PM PDT 24 |
4252143134 ps |
| T867 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2235878548 |
|
|
Jul 17 07:26:34 PM PDT 24 |
Jul 17 07:27:22 PM PDT 24 |
8327787903 ps |
| T868 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1998091565 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:20:57 PM PDT 24 |
45706631 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2788318884 |
|
|
Jul 17 07:20:48 PM PDT 24 |
Jul 17 07:21:02 PM PDT 24 |
30873576 ps |
| T870 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1819387233 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:38:50 PM PDT 24 |
11765398473 ps |
| T871 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1186608543 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:21:03 PM PDT 24 |
347973651 ps |
| T872 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3425149928 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:21:55 PM PDT 24 |
6427247953 ps |
| T873 |
/workspace/coverage/default/5.sram_ctrl_executable.550857833 |
|
|
Jul 17 07:20:50 PM PDT 24 |
Jul 17 07:55:48 PM PDT 24 |
29881319753 ps |
| T874 |
/workspace/coverage/default/16.sram_ctrl_partial_access.674102800 |
|
|
Jul 17 07:21:11 PM PDT 24 |
Jul 17 07:21:25 PM PDT 24 |
2591951615 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3592883073 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:23:29 PM PDT 24 |
20234125568 ps |
| T876 |
/workspace/coverage/default/13.sram_ctrl_stress_all.614381403 |
|
|
Jul 17 07:20:50 PM PDT 24 |
Jul 17 08:57:50 PM PDT 24 |
692997813682 ps |
| T877 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2387449882 |
|
|
Jul 17 07:24:07 PM PDT 24 |
Jul 17 07:26:54 PM PDT 24 |
2848167045 ps |
| T878 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3669389534 |
|
|
Jul 17 07:20:44 PM PDT 24 |
Jul 17 07:20:52 PM PDT 24 |
1353966756 ps |
| T879 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.853224972 |
|
|
Jul 17 07:20:36 PM PDT 24 |
Jul 17 07:26:51 PM PDT 24 |
112661636693 ps |
| T880 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2163918573 |
|
|
Jul 17 07:24:13 PM PDT 24 |
Jul 17 07:24:20 PM PDT 24 |
436204030 ps |
| T881 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3927171133 |
|
|
Jul 17 07:21:17 PM PDT 24 |
Jul 17 07:22:44 PM PDT 24 |
3172636083 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2900296695 |
|
|
Jul 17 07:24:19 PM PDT 24 |
Jul 17 07:30:52 PM PDT 24 |
7394065068 ps |
| T883 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1642486988 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:29:46 PM PDT 24 |
5717841530 ps |
| T884 |
/workspace/coverage/default/28.sram_ctrl_regwen.427188476 |
|
|
Jul 17 07:24:11 PM PDT 24 |
Jul 17 07:26:20 PM PDT 24 |
3198373706 ps |
| T885 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3973547712 |
|
|
Jul 17 07:24:13 PM PDT 24 |
Jul 17 07:36:42 PM PDT 24 |
13151380877 ps |
| T886 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2755842825 |
|
|
Jul 17 07:21:12 PM PDT 24 |
Jul 17 07:21:18 PM PDT 24 |
1355472723 ps |
| T887 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1859152700 |
|
|
Jul 17 07:21:13 PM PDT 24 |
Jul 17 07:21:17 PM PDT 24 |
25431486 ps |
| T888 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.114381783 |
|
|
Jul 17 07:24:18 PM PDT 24 |
Jul 17 07:28:33 PM PDT 24 |
21266925065 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3046874855 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:22:35 PM PDT 24 |
1980325042 ps |
| T890 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2533430753 |
|
|
Jul 17 07:27:07 PM PDT 24 |
Jul 17 07:29:10 PM PDT 24 |
6824688253 ps |
| T891 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1999835687 |
|
|
Jul 17 07:24:09 PM PDT 24 |
Jul 17 07:26:49 PM PDT 24 |
27629918478 ps |
| T892 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.51281553 |
|
|
Jul 17 07:20:50 PM PDT 24 |
Jul 17 07:25:14 PM PDT 24 |
3612455291 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.527661159 |
|
|
Jul 17 07:24:01 PM PDT 24 |
Jul 17 07:31:51 PM PDT 24 |
37870100361 ps |
| T894 |
/workspace/coverage/default/14.sram_ctrl_executable.762534996 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:28:03 PM PDT 24 |
23605826397 ps |
| T895 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1228511059 |
|
|
Jul 17 07:20:52 PM PDT 24 |
Jul 17 07:21:26 PM PDT 24 |
3855772458 ps |
| T896 |
/workspace/coverage/default/29.sram_ctrl_partial_access.209747309 |
|
|
Jul 17 07:24:07 PM PDT 24 |
Jul 17 07:24:28 PM PDT 24 |
1352332340 ps |
| T897 |
/workspace/coverage/default/42.sram_ctrl_regwen.1913391765 |
|
|
Jul 17 07:25:36 PM PDT 24 |
Jul 17 07:28:17 PM PDT 24 |
5556968023 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.218731138 |
|
|
Jul 17 07:24:20 PM PDT 24 |
Jul 17 07:25:37 PM PDT 24 |
4730443741 ps |
| T899 |
/workspace/coverage/default/33.sram_ctrl_regwen.1659118845 |
|
|
Jul 17 07:24:13 PM PDT 24 |
Jul 17 07:27:31 PM PDT 24 |
2046732566 ps |
| T900 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1845206229 |
|
|
Jul 17 07:24:08 PM PDT 24 |
Jul 17 07:24:38 PM PDT 24 |
1876629100 ps |
| T901 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2866862344 |
|
|
Jul 17 07:24:18 PM PDT 24 |
Jul 17 07:28:35 PM PDT 24 |
8704827372 ps |
| T902 |
/workspace/coverage/default/11.sram_ctrl_stress_all.868917578 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:47:54 PM PDT 24 |
19567241788 ps |
| T903 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1585802820 |
|
|
Jul 17 07:20:48 PM PDT 24 |
Jul 17 07:21:24 PM PDT 24 |
2722317189 ps |
| T904 |
/workspace/coverage/default/19.sram_ctrl_regwen.3201669475 |
|
|
Jul 17 07:21:04 PM PDT 24 |
Jul 17 07:29:02 PM PDT 24 |
9024177065 ps |
| T905 |
/workspace/coverage/default/35.sram_ctrl_bijection.4156781487 |
|
|
Jul 17 07:24:22 PM PDT 24 |
Jul 17 07:43:55 PM PDT 24 |
51630652198 ps |
| T906 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3042495498 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:21:10 PM PDT 24 |
8207157358 ps |
| T907 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3704496075 |
|
|
Jul 17 07:20:43 PM PDT 24 |
Jul 17 07:26:18 PM PDT 24 |
15112428979 ps |
| T908 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2435439664 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:20:58 PM PDT 24 |
1407827082 ps |
| T909 |
/workspace/coverage/default/1.sram_ctrl_smoke.719049095 |
|
|
Jul 17 07:20:42 PM PDT 24 |
Jul 17 07:22:16 PM PDT 24 |
886377986 ps |
| T910 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3464428021 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:26:11 PM PDT 24 |
51260099730 ps |
| T911 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3945854713 |
|
|
Jul 17 07:25:35 PM PDT 24 |
Jul 17 07:25:44 PM PDT 24 |
1353019470 ps |
| T912 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2843041270 |
|
|
Jul 17 07:21:02 PM PDT 24 |
Jul 17 07:21:50 PM PDT 24 |
7048424556 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_smoke.2302726987 |
|
|
Jul 17 07:20:48 PM PDT 24 |
Jul 17 07:21:12 PM PDT 24 |
464303383 ps |
| T914 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.26812024 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:21:07 PM PDT 24 |
698131407 ps |
| T915 |
/workspace/coverage/default/42.sram_ctrl_executable.101042492 |
|
|
Jul 17 07:25:42 PM PDT 24 |
Jul 17 07:39:08 PM PDT 24 |
22097284728 ps |
| T916 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1256609901 |
|
|
Jul 17 07:24:09 PM PDT 24 |
Jul 17 07:37:03 PM PDT 24 |
34868153222 ps |
| T917 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2439917517 |
|
|
Jul 17 07:21:11 PM PDT 24 |
Jul 17 07:21:14 PM PDT 24 |
14585590 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3350107241 |
|
|
Jul 17 07:20:49 PM PDT 24 |
Jul 17 07:21:09 PM PDT 24 |
2912463960 ps |
| T919 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3370701468 |
|
|
Jul 17 07:25:36 PM PDT 24 |
Jul 17 07:40:19 PM PDT 24 |
43827427063 ps |
| T920 |
/workspace/coverage/default/18.sram_ctrl_regwen.3287187579 |
|
|
Jul 17 07:21:11 PM PDT 24 |
Jul 17 07:32:32 PM PDT 24 |
25056107231 ps |
| T921 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.688685090 |
|
|
Jul 17 07:26:34 PM PDT 24 |
Jul 17 07:28:32 PM PDT 24 |
768303069 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1658338301 |
|
|
Jul 17 07:21:13 PM PDT 24 |
Jul 17 07:22:18 PM PDT 24 |
21041243496 ps |
| T923 |
/workspace/coverage/default/4.sram_ctrl_executable.1218803775 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:24:21 PM PDT 24 |
53809874014 ps |
| T924 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3975386887 |
|
|
Jul 17 07:20:46 PM PDT 24 |
Jul 17 07:30:49 PM PDT 24 |
24468761972 ps |
| T925 |
/workspace/coverage/default/22.sram_ctrl_bijection.3020888594 |
|
|
Jul 17 07:22:22 PM PDT 24 |
Jul 17 08:01:20 PM PDT 24 |
125701283908 ps |
| T926 |
/workspace/coverage/default/46.sram_ctrl_regwen.1773861914 |
|
|
Jul 17 07:26:02 PM PDT 24 |
Jul 17 07:39:20 PM PDT 24 |
17439151163 ps |
| T927 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2493790762 |
|
|
Jul 17 07:22:24 PM PDT 24 |
Jul 17 07:22:32 PM PDT 24 |
691745770 ps |
| T928 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2606850457 |
|
|
Jul 17 07:20:42 PM PDT 24 |
Jul 17 07:23:12 PM PDT 24 |
16801471920 ps |
| T929 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.877453586 |
|
|
Jul 17 07:24:01 PM PDT 24 |
Jul 17 07:49:58 PM PDT 24 |
21137897266 ps |
| T930 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1440874544 |
|
|
Jul 17 07:20:45 PM PDT 24 |
Jul 17 07:21:15 PM PDT 24 |
907609405 ps |
| T931 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.104978484 |
|
|
Jul 17 07:26:35 PM PDT 24 |
Jul 17 07:28:37 PM PDT 24 |
2895845987 ps |
| T932 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3977273553 |
|
|
Jul 17 07:20:44 PM PDT 24 |
Jul 17 07:25:56 PM PDT 24 |
5086152614 ps |
| T933 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3249862094 |
|
|
Jul 17 07:22:22 PM PDT 24 |
Jul 17 07:39:52 PM PDT 24 |
15678612216 ps |
| T934 |
/workspace/coverage/default/17.sram_ctrl_regwen.36530149 |
|
|
Jul 17 07:21:10 PM PDT 24 |
Jul 17 07:32:01 PM PDT 24 |
10508828323 ps |
| T935 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.33703791 |
|
|
Jul 17 07:20:47 PM PDT 24 |
Jul 17 07:22:13 PM PDT 24 |
2576989465 ps |
| T936 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2941532751 |
|
|
Jul 17 07:20:46 PM PDT 24 |
Jul 17 07:26:58 PM PDT 24 |
57002001590 ps |
| T937 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1466608598 |
|
|
Jul 17 07:22:21 PM PDT 24 |
Jul 17 07:28:34 PM PDT 24 |
125654211813 ps |
| T938 |
/workspace/coverage/default/16.sram_ctrl_smoke.2348259251 |
|
|
Jul 17 07:21:11 PM PDT 24 |
Jul 17 07:22:49 PM PDT 24 |
3688958386 ps |
| T939 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2738718760 |
|
|
Jul 17 07:22:22 PM PDT 24 |
Jul 17 07:27:10 PM PDT 24 |
40557106214 ps |
| T940 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2438220438 |
|
|
Jul 17 07:24:21 PM PDT 24 |
Jul 17 07:31:18 PM PDT 24 |
13563341985 ps |
| T941 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3223098872 |
|
|
Jul 17 07:24:06 PM PDT 24 |
Jul 17 07:24:08 PM PDT 24 |
18927767 ps |
| T942 |
/workspace/coverage/default/21.sram_ctrl_bijection.1701990055 |
|
|
Jul 17 07:22:22 PM PDT 24 |
Jul 17 07:59:36 PM PDT 24 |
62373049407 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3747459012 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:37 PM PDT 24 |
364779064 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4003940229 |
|
|
Jul 17 07:13:07 PM PDT 24 |
Jul 17 07:13:26 PM PDT 24 |
229431192 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1828848756 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:30 PM PDT 24 |
1615654852 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4240054255 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:14:24 PM PDT 24 |
7425195653 ps |
| T72 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1417661161 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:14:05 PM PDT 24 |
15405131778 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3896540673 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
104631717 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4142023247 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
164005205 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2777301624 |
|
|
Jul 17 07:13:05 PM PDT 24 |
Jul 17 07:13:14 PM PDT 24 |
97260021 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3741640393 |
|
|
Jul 17 07:13:23 PM PDT 24 |
Jul 17 07:14:40 PM PDT 24 |
14681466775 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3720056536 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:52 PM PDT 24 |
3821248334 ps |
| T111 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.367186864 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
18638671 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3373964758 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:57 PM PDT 24 |
3784070568 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3489095056 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
40794833 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3179675581 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:25 PM PDT 24 |
37382118 ps |
| T67 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2361654677 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:25 PM PDT 24 |
107325170 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3034446632 |
|
|
Jul 17 07:13:07 PM PDT 24 |
Jul 17 07:13:23 PM PDT 24 |
620404448 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.191280504 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:38 PM PDT 24 |
365271654 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1487215499 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:26 PM PDT 24 |
1927106312 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2033700568 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:45 PM PDT 24 |
359905472 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2630325822 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:45 PM PDT 24 |
1333669457 ps |
| T69 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1280252590 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:26 PM PDT 24 |
522693051 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1144892300 |
|
|
Jul 17 07:13:19 PM PDT 24 |
Jul 17 07:13:51 PM PDT 24 |
1421571851 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.24412837 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:25 PM PDT 24 |
47606222 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.676955152 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:25 PM PDT 24 |
40220287 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3454659123 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
39421405 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.998159506 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:33 PM PDT 24 |
19615519 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1100201941 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:47 PM PDT 24 |
922922413 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3977924614 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:39 PM PDT 24 |
39747385 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2194568435 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:14:02 PM PDT 24 |
26572662476 ps |
| T84 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3276557073 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:50 PM PDT 24 |
7392071603 ps |
| T118 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3618749407 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:36 PM PDT 24 |
195984407 ps |
| T104 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3692433069 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:33 PM PDT 24 |
18547550 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1069129664 |
|
|
Jul 17 07:13:15 PM PDT 24 |
Jul 17 07:13:46 PM PDT 24 |
1435266412 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.959735739 |
|
|
Jul 17 07:13:06 PM PDT 24 |
Jul 17 07:13:18 PM PDT 24 |
354095240 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3248406114 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:41 PM PDT 24 |
105136696 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.203210712 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:29 PM PDT 24 |
146986548 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3522803620 |
|
|
Jul 17 07:13:05 PM PDT 24 |
Jul 17 07:13:14 PM PDT 24 |
24547082 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1102898304 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:41 PM PDT 24 |
61380073 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3314388467 |
|
|
Jul 17 07:13:15 PM PDT 24 |
Jul 17 07:13:46 PM PDT 24 |
84688779 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4282744800 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:37 PM PDT 24 |
142085715 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.372911430 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
19119439 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1620880130 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:40 PM PDT 24 |
123409782 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1413193430 |
|
|
Jul 17 07:13:07 PM PDT 24 |
Jul 17 07:14:12 PM PDT 24 |
7386675638 ps |
| T120 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1388481482 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:38 PM PDT 24 |
744405653 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3282374669 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:46 PM PDT 24 |
734521527 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.808460432 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
83183840 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4064327205 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:35 PM PDT 24 |
68640048 ps |
| T123 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4287136871 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:35 PM PDT 24 |
210065397 ps |
| T94 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3021943178 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:14:09 PM PDT 24 |
6389802318 ps |
| T967 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1479459714 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:33 PM PDT 24 |
42356771 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4146685561 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:41 PM PDT 24 |
20958764 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3409702385 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
176940981 ps |
| T969 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3736833575 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
20321442 ps |
| T128 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2335161715 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:38 PM PDT 24 |
272711721 ps |
| T970 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3393278986 |
|
|
Jul 17 07:13:04 PM PDT 24 |
Jul 17 07:13:10 PM PDT 24 |
19188375 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.322537354 |
|
|
Jul 17 07:13:04 PM PDT 24 |
Jul 17 07:13:09 PM PDT 24 |
264354549 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.928348888 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:32 PM PDT 24 |
353725010 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3538051288 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:37 PM PDT 24 |
47127423 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3820263968 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:33 PM PDT 24 |
23082090 ps |
| T119 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.798112502 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
98677468 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2631638102 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:14:23 PM PDT 24 |
28147414823 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2063387540 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:27 PM PDT 24 |
194984649 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1693951813 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
351710272 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2431613066 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:35 PM PDT 24 |
196508904 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3377151446 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:41 PM PDT 24 |
389873622 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.732651724 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:32 PM PDT 24 |
11738373 ps |
| T99 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3625459432 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:29 PM PDT 24 |
15098521 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3363998591 |
|
|
Jul 17 07:13:12 PM PDT 24 |
Jul 17 07:13:37 PM PDT 24 |
12668458 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1177151758 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:25 PM PDT 24 |
21858123 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.85754966 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:14:27 PM PDT 24 |
14393733600 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.805749320 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:28 PM PDT 24 |
35127219 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.172683469 |
|
|
Jul 17 07:13:13 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
54464390 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.473070637 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:45 PM PDT 24 |
364237136 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.495219854 |
|
|
Jul 17 07:13:24 PM PDT 24 |
Jul 17 07:13:52 PM PDT 24 |
15634918 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.767723631 |
|
|
Jul 17 07:13:24 PM PDT 24 |
Jul 17 07:13:51 PM PDT 24 |
194437559 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3457259090 |
|
|
Jul 17 07:13:18 PM PDT 24 |
Jul 17 07:13:47 PM PDT 24 |
54993550 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2978936679 |
|
|
Jul 17 07:13:07 PM PDT 24 |
Jul 17 07:13:21 PM PDT 24 |
56466626 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.655246771 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:31 PM PDT 24 |
33787308 ps |
| T988 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3147189999 |
|
|
Jul 17 07:13:06 PM PDT 24 |
Jul 17 07:13:45 PM PDT 24 |
4092226722 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1102362791 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
23623842 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4025135969 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:35 PM PDT 24 |
83288159 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3258850728 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:37 PM PDT 24 |
1525894364 ps |
| T126 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.215467782 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:32 PM PDT 24 |
183544919 ps |
| T97 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3416288422 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:51 PM PDT 24 |
15407631923 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2877772468 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:29 PM PDT 24 |
13870752 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2339905201 |
|
|
Jul 17 07:13:11 PM PDT 24 |
Jul 17 07:13:35 PM PDT 24 |
208903014 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1962953726 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:44 PM PDT 24 |
188550702 ps |
| T98 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2178944472 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:13:52 PM PDT 24 |
7516869612 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3615349384 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:34 PM PDT 24 |
72937276 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.467761 |
|
|
Jul 17 07:13:18 PM PDT 24 |
Jul 17 07:13:46 PM PDT 24 |
61448030 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.252115395 |
|
|
Jul 17 07:13:18 PM PDT 24 |
Jul 17 07:13:50 PM PDT 24 |
1467231340 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2408411082 |
|
|
Jul 17 07:13:08 PM PDT 24 |
Jul 17 07:13:27 PM PDT 24 |
965455077 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1496482954 |
|
|
Jul 17 07:13:14 PM PDT 24 |
Jul 17 07:13:42 PM PDT 24 |
17515290 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1013593219 |
|
|
Jul 17 07:13:24 PM PDT 24 |
Jul 17 07:13:51 PM PDT 24 |
38834106 ps |
| T122 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1810487384 |
|
|
Jul 17 07:13:18 PM PDT 24 |
Jul 17 07:13:47 PM PDT 24 |
486911165 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2525231050 |
|
|
Jul 17 07:13:09 PM PDT 24 |
Jul 17 07:14:15 PM PDT 24 |
7511360004 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.313061018 |
|
|
Jul 17 07:13:10 PM PDT 24 |
Jul 17 07:13:31 PM PDT 24 |
110965708 ps |