Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	365095758	1			T1	9448		T2	14110		T3	11696
instr_valid_dis	319931529	1			T1	9448		T2	14110		T3	11696
instr_en	33564222	1			T6	343554		T13	102996		T24	185500

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14929572	1			T6	31064		T13	36238		T24	20042
sram_ifetch_valid_disable	324694488	1			T1	9448		T2	14110		T3	11696
sram_ifetch_enable	25471698	1			T6	168852		T13	176384		T24	204262

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	365095758	1			T1	9448		T2	14110		T3	11696
hw_debug_en_valid_off	327800688	1			T1	9448		T2	14110		T3	11696
hw_debug_en_on	24703142	1			T6	152018		T13	105544		T24	130600

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	324694488	1			T1	9448		T2	14110		T3	11696
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	307678345	1			T1	9448		T2	14110		T3	11696
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13756786	1			T6	143638		T13	9062		T24	103804
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7693540	1			T24	20042		T145	17424		T146	67904
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1818490	1			T24	20042		T145	17424		T146	59924
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1880150	1			T147	1766		T22	50862		T81	4798
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5183430	1			T6	31064		T13	7684		T26	1026
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1360142	1			T26	1026		T147	24890		T21	14416
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3112770	1			T6	31064		T21	4500		T81	44012
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8592028	1			T6	91204		T13	5344		T24	8834
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3241760	1			T13	5344		T145	69206		T147	60224
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4264192	1			T6	91204		T24	8834		T145	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13887766	1			T6	168852		T13	93934		T24	81696
lc_exec_en	10927684	1			T6	29750		T13	92516		T24	121766
valid_exec_dis	318762938	1			T1	9448		T2	14110		T3	11696
invalid_exec_dis	40401270	1			T6	199916		T13	212622		T24	224304