Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	152553781	1			T1	893		T2	1281		T3	1107
triple_byte_access	2833891	1			T1	804		T2	1158		T3	927
halfword_access	4348594	1			T1	1134		T2	1692		T3	1457
byte_access	6063775	1			T1	1502		T2	2355		T3	1888
zero_access	1824357	1			T1	391		T2	569		T3	469

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83666022

1

T1

2351

T2

3529

T3

2956

auto[1]

83958376

1

T1

2373

T2

3526

T3

2892

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75982407	1			T1	436		T2	649		T3	590
auto[0]	triple_byte_access	1355298	1			T1	385		T2	563		T3	462
auto[0]	halfword_access	2130561	1			T1	587		T2	867		T3	768
auto[0]	byte_access	3111715	1			T1	747		T2	1178		T3	922
auto[0]	zero_access	1086041	1			T1	196		T2	272		T3	214
auto[1]	word_access	76571374	1			T1	457		T2	632		T3	517
auto[1]	triple_byte_access	1478593	1			T1	419		T2	595		T3	465
auto[1]	halfword_access	2218033	1			T1	547		T2	825		T3	689
auto[1]	byte_access	2952060	1			T1	755		T2	1177		T3	966
auto[1]	zero_access	738316	1			T1	195		T2	297		T3	255