Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	351095654	1			T1	548428		T3	393212		T4	8186
instr_valid_dis	317698007	1			T1	548428		T3	393212		T4	8186
instr_en	22295114	1			T15	110462		T25	193354		T26	42206

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9962882	1			T15	148188		T25	51632		T43	18948
sram_ifetch_valid_disable	313712306	1			T1	548428		T3	393212		T4	8186
sram_ifetch_enable	27420466	1			T15	250720		T25	114470		T26	7474

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	351095654	1			T1	548428		T3	393212		T4	8186
hw_debug_en_valid_off	310741198	1			T1	548428		T3	393212		T4	8186
hw_debug_en_on	24086136	1			T15	299180		T25	141968		T43	74748

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	313712306	1			T1	548428		T3	393212		T4	8186
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	300628393	1			T1	548428		T3	393212		T4	8186
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9876420	1			T15	15562		T25	74178		T26	42108
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4047750	1			T15	92376		T25	36840		T6	49396
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1926362	1			T15	66802		T6	24810		T7	140246
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1597788	1			T15	25574		T25	36840		T6	17122
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3988556	1			T15	28170		T43	18948		T128	100410
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1804258	1			T15	17368		T128	60520		T6	312
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1522646	1			T15	10802		T43	18948		T6	18246
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8370798	1			T15	157998		T25	84376		T44	10854
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3870214	1			T15	97128		T25	40766		T44	10854
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3242544	1			T15	10918		T25	16240		T128	98942

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8781236	1			T15	58524		T25	76108		T26	98
lc_exec_en	11726782	1			T15	113012		T25	57592		T43	55800
valid_exec_dis	310307002	1			T1	548428		T3	393212		T4	8186
invalid_exec_dis	37383348	1			T15	398908		T25	166102		T26	7474