Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145732183	1			T1	249387		T3	196606		T4	3399
triple_byte_access	2851464	1			T1	4855		T4	146		T5	1057
halfword_access	4367870	1			T1	7543		T4	213		T5	1542
byte_access	6095098	1			T1	9924		T4	266		T5	1999
zero_access	1828835	1			T1	2505		T4	69		T5	461

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80184455

1

T1

136782

T3

65536

T4

2109

auto[1]

80690995

1

T1

137432

T3

131070

T4

1984

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72477737	1			T1	124307		T3	65536		T4	1743
auto[0]	triple_byte_access	1363174	1			T1	2455		T4	71		T5	533
auto[0]	halfword_access	2136957	1			T1	3802		T4	111		T5	759
auto[0]	byte_access	3121378	1			T1	4982		T4	149		T5	986
auto[0]	zero_access	1085209	1			T1	1236		T4	35		T5	215
auto[1]	word_access	73254446	1			T1	125080		T3	131070		T4	1656
auto[1]	triple_byte_access	1488290	1			T1	2400		T4	75		T5	524
auto[1]	halfword_access	2230913	1			T1	3741		T4	102		T5	783
auto[1]	byte_access	2973720	1			T1	4942		T4	117		T5	1013
auto[1]	zero_access	743626	1			T1	1269		T4	34		T5	246