Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	359009986	1			T2	5964		T3	270472		T4	11458
instr_valid_dis	321496280	1			T2	5964		T3	68424		T4	11458
instr_en	28394791	1			T3	185944		T7	320994		T12	397626

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10791206	1			T3	70570		T7	72998		T12	33214
sram_ifetch_valid_disable	314734936	1			T2	5964		T3	110150		T4	11458
sram_ifetch_enable	33483844	1			T3	89752		T7	88192		T12	258628

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	359009986	1			T2	5964		T3	270472		T4	11458
hw_debug_en_valid_off	313549514	1			T2	5964		T3	81776		T4	11458
hw_debug_en_on	25914236	1			T3	146144		T7	87868		T12	156282

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	314734936	1			T2	5964		T3	110150		T4	11458
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	299554046	1			T2	5964		T3	21936		T4	11458
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10858783	1			T3	75292		T7	159804		T12	105784
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4470034	1			T3	52646		T12	33214		T19	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1591420	1			T69	37158		T20	16512		T136	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2079758	1			T3	52646		T12	33214		T19	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4133922	1			T7	9506		T19	50838		T68	38046
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1958626	1			T69	5946		T135	22926		T35	43504
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1651912	1			T7	9506		T19	50838		T68	38046
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9239350	1			T3	77824		T7	38538		T12	52162
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4139866	1			T3	2532		T7	7472		T25	12894
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3803234	1			T3	75292		T7	31066		T12	52162

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12887520	1			T3	40082		T7	88192		T12	258628
lc_exec_en	12540964	1			T3	68320		T7	39824		T12	104120
valid_exec_dis	314341242	1			T2	5964		T3	57368		T4	11458
invalid_exec_dis	44275050	1			T3	160322		T7	161190		T12	291842