Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	149486717	1			T2	163		T3	59803		T4	5238
triple_byte_access	2798006	1			T2	2		T3	1227		T4	87
halfword_access	4290851	1			T2	3		T3	1890		T4	152
byte_access	5982632	1			T2	4		T3	2361		T4	199
zero_access	1793394	1			T2	1		T3	584		T4	53

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81998567

1

T2

94

T3

38779

T4

2884

auto[1]

82353033

1

T2

79

T3

27086

T4

2845

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	74425664	1			T2	90		T3	35218		T4	2645
auto[0]	triple_byte_access	1338365	1			T2	2		T3	735		T4	45
auto[0]	halfword_access	2104041	1			T2	1		T3	1087		T4	71
auto[0]	byte_access	3066504	1			T2	1		T3	1399		T4	96
auto[0]	zero_access	1063993	1			T3	340		T4	27		T7	430
auto[1]	word_access	75061053	1			T2	73		T3	24585		T4	2593
auto[1]	triple_byte_access	1459641	1			T3	492		T4	42		T7	598
auto[1]	halfword_access	2186810	1			T2	2		T3	803		T4	81
auto[1]	byte_access	2916128	1			T2	3		T3	962		T4	103
auto[1]	zero_access	729401	1			T2	1		T3	244		T4	26