Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	371752790	1			T1	318686		T2	5776		T3	306386
instr_valid_dis	304192865	1			T1	318686		T2	5776		T3	306386
instr_en	50111563	1			T6	491770		T23	94088		T24	53492

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12727822	1			T6	184334		T23	15572		T24	16828
sram_ifetch_valid_disable	319319616	1			T1	318686		T2	5776		T3	306386
sram_ifetch_enable	39705352	1			T6	239392		T23	97378		T24	101162

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	371752790	1			T1	318686		T2	5776		T3	306386
hw_debug_en_valid_off	312658262	1			T1	318686		T2	5776		T3	306386
hw_debug_en_on	41629756	1			T6	267018		T23	39166		T24	78648

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	319319616	1			T1	318686		T2	5776		T3	306386
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	286778145	1			T1	318686		T2	5776		T3	306386
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	25441195	1			T6	155524		T23	32932		T24	10176
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5733382	1			T6	98672		T23	15572		T134	47534
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2346488	1			T6	7046		T134	14814		T18	17530
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2664100	1			T6	91626		T23	15572		T134	32720
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4768004	1			T6	85662		T24	16828		T18	92546
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1878832	1			T24	11504		T68	100		T69	37660
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2072184	1			T6	85662		T24	5324		T18	21092
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	20083702	1			T6	147968		T24	70		T40	71384
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4883352	1			T6	72698		T24	70		T134	48302
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	11329102	1			T6	60328		T134	67166		T18	101755

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	19002084	1			T6	158958		T23	45584		T24	37992
lc_exec_en	16778050	1			T6	33388		T23	39166		T24	61750
valid_exec_dis	303674504	1			T1	318686		T2	5776		T3	306386
invalid_exec_dis	52433174	1			T6	423726		T23	112950		T24	117990