Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153969208	1			T1	144751		T2	225		T3	27907
triple_byte_access	2875973	1			T1	2848		T2	3		T3	25135
halfword_access	4404063	1			T1	4423		T2	9		T3	37416
byte_access	6138902	1			T1	5822		T2	9		T3	50460
zero_access	1839641	1			T1	1499		T2	4		T3	12275

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84625082

1

T1

79582

T2

121

T3

76582

auto[1]

84602705

1

T1

79761

T2

129

T3

76611

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76840333	1			T1	72250		T2	108		T3	13934
auto[0]	triple_byte_access	1380755	1			T1	1426		T2	1		T3	12629
auto[0]	halfword_access	2160687	1			T1	2209		T2	5		T3	18714
auto[0]	byte_access	3150447	1			T1	2913		T2	5		T3	25199
auto[0]	zero_access	1092860	1			T1	784		T2	2		T3	6106
auto[1]	word_access	77128875	1			T1	72501		T2	117		T3	13973
auto[1]	triple_byte_access	1495218	1			T1	1422		T2	2		T3	12506
auto[1]	halfword_access	2243376	1			T1	2214		T2	4		T3	18702
auto[1]	byte_access	2988455	1			T1	2909		T2	4		T3	25261
auto[1]	zero_access	746781	1			T1	715		T2	2		T3	6169