Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	312530170	1			T1	164582		T2	18842		T3	33960
instr_valid_dis	272016212	1			T1	164582		T2	18842		T3	33960
instr_en	30152066	1			T22	376494		T24	620384		T45	243342

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13571238	1			T22	92438		T18	66142		T24	383338
sram_ifetch_valid_disable	273844346	1			T1	164582		T2	18842		T3	33960
sram_ifetch_enable	25114586	1			T22	140270		T18	96542		T24	301522

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	312530170	1			T1	164582		T2	18842		T3	33960
hw_debug_en_valid_off	274323680	1			T1	164582		T2	18842		T3	33960
hw_debug_en_on	26844458	1			T22	125812		T18	210430		T24	291936

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	273844346	1			T1	164582		T2	18842		T3	33960
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	258835382	1			T1	164582		T2	18842		T3	33960
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10856562	1			T22	143786		T24	85888		T45	50722
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5027602	1			T22	59182		T18	3224		T24	22578
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1551002	1			T75	11708		T47	131270		T144	3568
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2444374	1			T22	59182		T24	5122		T45	53982
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6207502	1			T18	62918		T24	35314		T45	13588
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1394000	1			T47	4214		T145	27554		T146	11352
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3831004	1			T24	14124		T45	13588		T75	81774
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9904544	1			T22	93652		T18	77364		T24	48998
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4402836	1			T144	117248		T145	43520		T147	42926
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4046320	1			T22	93652		T24	29536		T45	32918

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11858410	1			T22	140270		T24	209804		T45	107942
lc_exec_en	10732412	1			T22	32160		T18	70148		T24	207624
valid_exec_dis	268130714	1			T1	164582		T2	18842		T3	33960
invalid_exec_dis	38685824	1			T22	232708		T18	162684		T24	684860