Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	126783626	1			T1	74867		T2	1661		T3	1169
triple_byte_access	2818990	1			T1	1522		T2	1622		T3	26
halfword_access	4321018	1			T1	2247		T2	2322		T3	34
byte_access	6031527	1			T1	2878		T2	3060		T3	40
zero_access	1813738	1			T1	777		T2	756		T3	9

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70744226

1

T1

41052

T2

4787

T3

642

auto[1]

71024673

1

T1

41239

T2

4634

T3

636

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	63116236	1			T1	37318		T2	849		T3	580
auto[0]	triple_byte_access	1346419	1			T1	749		T2	835		T3	16
auto[0]	halfword_access	2113267	1			T1	1110		T2	1182		T3	17
auto[0]	byte_access	3090020	1			T1	1470		T2	1544		T3	20
auto[0]	zero_access	1078284	1			T1	405		T2	377		T3	9
auto[1]	word_access	63667390	1			T1	37549		T2	812		T3	589
auto[1]	triple_byte_access	1472571	1			T1	773		T2	787		T3	10
auto[1]	halfword_access	2207751	1			T1	1137		T2	1140		T3	17
auto[1]	byte_access	2941507	1			T1	1408		T2	1516		T3	20
auto[1]	zero_access	735454	1			T1	372		T2	379		T4	158