| T796 |
/workspace/coverage/default/33.sram_ctrl_bijection.656930600 |
|
|
Aug 06 07:21:39 PM PDT 24 |
Aug 06 07:33:03 PM PDT 24 |
86485468965 ps |
| T797 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1434680833 |
|
|
Aug 06 07:17:46 PM PDT 24 |
Aug 06 07:20:39 PM PDT 24 |
809860161 ps |
| T798 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2736201154 |
|
|
Aug 06 07:20:31 PM PDT 24 |
Aug 06 07:20:43 PM PDT 24 |
2269392043 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_regwen.1678785220 |
|
|
Aug 06 07:20:12 PM PDT 24 |
Aug 06 07:33:35 PM PDT 24 |
2217929076 ps |
| T800 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1518688177 |
|
|
Aug 06 07:19:29 PM PDT 24 |
Aug 06 07:20:33 PM PDT 24 |
5263334299 ps |
| T801 |
/workspace/coverage/default/7.sram_ctrl_smoke.960567763 |
|
|
Aug 06 07:18:09 PM PDT 24 |
Aug 06 07:18:18 PM PDT 24 |
796043791 ps |
| T802 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2342830494 |
|
|
Aug 06 07:23:23 PM PDT 24 |
Aug 06 07:23:29 PM PDT 24 |
3166096213 ps |
| T803 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2412338722 |
|
|
Aug 06 07:18:20 PM PDT 24 |
Aug 06 07:18:45 PM PDT 24 |
749221847 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4291030890 |
|
|
Aug 06 07:19:06 PM PDT 24 |
Aug 06 07:19:41 PM PDT 24 |
4636925922 ps |
| T805 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4100471266 |
|
|
Aug 06 07:24:39 PM PDT 24 |
Aug 06 07:27:07 PM PDT 24 |
4518796653 ps |
| T806 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4028986881 |
|
|
Aug 06 07:21:10 PM PDT 24 |
Aug 06 07:21:14 PM PDT 24 |
1399981814 ps |
| T28 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3902482569 |
|
|
Aug 06 07:18:02 PM PDT 24 |
Aug 06 07:18:04 PM PDT 24 |
201966470 ps |
| T807 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1577567541 |
|
|
Aug 06 07:17:45 PM PDT 24 |
Aug 06 07:17:49 PM PDT 24 |
1358232169 ps |
| T808 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.445576638 |
|
|
Aug 06 07:22:33 PM PDT 24 |
Aug 06 07:25:13 PM PDT 24 |
779075424 ps |
| T809 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3014535364 |
|
|
Aug 06 07:18:29 PM PDT 24 |
Aug 06 07:18:38 PM PDT 24 |
4786573266 ps |
| T810 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3377035539 |
|
|
Aug 06 07:18:39 PM PDT 24 |
Aug 06 08:48:27 PM PDT 24 |
36754026685 ps |
| T811 |
/workspace/coverage/default/17.sram_ctrl_regwen.2805370034 |
|
|
Aug 06 07:19:05 PM PDT 24 |
Aug 06 07:20:48 PM PDT 24 |
11507178798 ps |
| T812 |
/workspace/coverage/default/36.sram_ctrl_smoke.3794918509 |
|
|
Aug 06 07:22:16 PM PDT 24 |
Aug 06 07:22:38 PM PDT 24 |
5815554802 ps |
| T813 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.368626019 |
|
|
Aug 06 07:23:40 PM PDT 24 |
Aug 06 07:38:27 PM PDT 24 |
29546122443 ps |
| T814 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1300754632 |
|
|
Aug 06 07:17:46 PM PDT 24 |
Aug 06 07:19:28 PM PDT 24 |
6376868058 ps |
| T815 |
/workspace/coverage/default/32.sram_ctrl_bijection.219901803 |
|
|
Aug 06 07:21:35 PM PDT 24 |
Aug 06 08:00:19 PM PDT 24 |
130835329981 ps |
| T816 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2369683318 |
|
|
Aug 06 07:19:04 PM PDT 24 |
Aug 06 07:19:05 PM PDT 24 |
11579080 ps |
| T817 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.196856185 |
|
|
Aug 06 07:18:02 PM PDT 24 |
Aug 06 07:19:23 PM PDT 24 |
952686250 ps |
| T818 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.833091131 |
|
|
Aug 06 07:18:41 PM PDT 24 |
Aug 06 07:20:18 PM PDT 24 |
12791053521 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_bijection.1997348571 |
|
|
Aug 06 07:18:42 PM PDT 24 |
Aug 06 07:45:19 PM PDT 24 |
47130183020 ps |
| T820 |
/workspace/coverage/default/15.sram_ctrl_smoke.1732696992 |
|
|
Aug 06 07:18:41 PM PDT 24 |
Aug 06 07:18:59 PM PDT 24 |
5274657986 ps |
| T821 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3694483969 |
|
|
Aug 06 07:18:43 PM PDT 24 |
Aug 06 07:21:18 PM PDT 24 |
4088465410 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2634969232 |
|
|
Aug 06 07:18:11 PM PDT 24 |
Aug 06 07:23:50 PM PDT 24 |
11062944865 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2286913348 |
|
|
Aug 06 07:22:48 PM PDT 24 |
Aug 06 07:25:16 PM PDT 24 |
3372505048 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_bijection.4247014574 |
|
|
Aug 06 07:21:23 PM PDT 24 |
Aug 06 07:51:20 PM PDT 24 |
82450430580 ps |
| T825 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2807322140 |
|
|
Aug 06 07:19:33 PM PDT 24 |
Aug 06 07:23:34 PM PDT 24 |
38362724735 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1061908568 |
|
|
Aug 06 07:18:04 PM PDT 24 |
Aug 06 07:23:58 PM PDT 24 |
13645068942 ps |
| T827 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2859480647 |
|
|
Aug 06 07:22:27 PM PDT 24 |
Aug 06 07:23:00 PM PDT 24 |
1041552682 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2036492196 |
|
|
Aug 06 07:24:23 PM PDT 24 |
Aug 06 07:29:33 PM PDT 24 |
14895586937 ps |
| T829 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1240257112 |
|
|
Aug 06 07:18:25 PM PDT 24 |
Aug 06 07:21:05 PM PDT 24 |
5415249288 ps |
| T830 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3264973965 |
|
|
Aug 06 07:18:30 PM PDT 24 |
Aug 06 07:18:53 PM PDT 24 |
793649275 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.145806103 |
|
|
Aug 06 07:18:42 PM PDT 24 |
Aug 06 07:19:24 PM PDT 24 |
758688471 ps |
| T832 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3500901757 |
|
|
Aug 06 07:24:06 PM PDT 24 |
Aug 06 07:24:38 PM PDT 24 |
5204243313 ps |
| T833 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2315750412 |
|
|
Aug 06 07:19:51 PM PDT 24 |
Aug 06 07:20:04 PM PDT 24 |
1407316992 ps |
| T834 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2105385596 |
|
|
Aug 06 07:18:06 PM PDT 24 |
Aug 06 07:25:05 PM PDT 24 |
14304444288 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_executable.538959734 |
|
|
Aug 06 07:24:38 PM PDT 24 |
Aug 06 07:46:15 PM PDT 24 |
53786764809 ps |
| T836 |
/workspace/coverage/default/3.sram_ctrl_regwen.2456155673 |
|
|
Aug 06 07:17:51 PM PDT 24 |
Aug 06 07:40:27 PM PDT 24 |
17622766784 ps |
| T837 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1629929687 |
|
|
Aug 06 07:19:46 PM PDT 24 |
Aug 06 07:19:55 PM PDT 24 |
926542927 ps |
| T838 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2518392702 |
|
|
Aug 06 07:24:22 PM PDT 24 |
Aug 06 07:26:10 PM PDT 24 |
91064827288 ps |
| T839 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.592676825 |
|
|
Aug 06 07:19:29 PM PDT 24 |
Aug 06 07:22:43 PM PDT 24 |
10151717407 ps |
| T840 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.313280951 |
|
|
Aug 06 07:20:11 PM PDT 24 |
Aug 06 07:34:55 PM PDT 24 |
33310454074 ps |
| T841 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3719252091 |
|
|
Aug 06 07:18:28 PM PDT 24 |
Aug 06 07:54:48 PM PDT 24 |
107581323833 ps |
| T842 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1388717268 |
|
|
Aug 06 07:24:39 PM PDT 24 |
Aug 06 07:43:35 PM PDT 24 |
14343499858 ps |
| T843 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2912051797 |
|
|
Aug 06 07:18:42 PM PDT 24 |
Aug 06 07:18:46 PM PDT 24 |
2594273829 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3545826116 |
|
|
Aug 06 07:20:11 PM PDT 24 |
Aug 06 08:49:01 PM PDT 24 |
528942001115 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.809448154 |
|
|
Aug 06 07:20:31 PM PDT 24 |
Aug 06 07:23:10 PM PDT 24 |
24712311951 ps |
| T846 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.597004063 |
|
|
Aug 06 07:19:05 PM PDT 24 |
Aug 06 07:33:22 PM PDT 24 |
13661954838 ps |
| T847 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1325118563 |
|
|
Aug 06 07:18:19 PM PDT 24 |
Aug 06 07:18:23 PM PDT 24 |
361678109 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.930703299 |
|
|
Aug 06 07:17:46 PM PDT 24 |
Aug 06 07:21:57 PM PDT 24 |
64846596546 ps |
| T849 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2557240351 |
|
|
Aug 06 07:19:48 PM PDT 24 |
Aug 06 07:25:11 PM PDT 24 |
77068394551 ps |
| T850 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.724044064 |
|
|
Aug 06 07:18:21 PM PDT 24 |
Aug 06 07:20:46 PM PDT 24 |
9729836369 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3479218714 |
|
|
Aug 06 07:18:41 PM PDT 24 |
Aug 06 07:21:29 PM PDT 24 |
9064972577 ps |
| T852 |
/workspace/coverage/default/25.sram_ctrl_stress_all.3510837883 |
|
|
Aug 06 07:20:13 PM PDT 24 |
Aug 06 08:01:50 PM PDT 24 |
140769126981 ps |
| T853 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3306048527 |
|
|
Aug 06 07:21:59 PM PDT 24 |
Aug 06 07:28:02 PM PDT 24 |
80200759039 ps |
| T854 |
/workspace/coverage/default/42.sram_ctrl_partial_access.3360617367 |
|
|
Aug 06 07:23:39 PM PDT 24 |
Aug 06 07:24:00 PM PDT 24 |
5539800624 ps |
| T855 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3014090526 |
|
|
Aug 06 07:21:10 PM PDT 24 |
Aug 06 07:23:41 PM PDT 24 |
2449715720 ps |
| T856 |
/workspace/coverage/default/7.sram_ctrl_executable.3375659784 |
|
|
Aug 06 07:18:08 PM PDT 24 |
Aug 06 07:31:05 PM PDT 24 |
28909150975 ps |
| T857 |
/workspace/coverage/default/31.sram_ctrl_stress_all.202101992 |
|
|
Aug 06 07:21:37 PM PDT 24 |
Aug 06 08:35:36 PM PDT 24 |
149984231451 ps |
| T858 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.108675784 |
|
|
Aug 06 07:18:40 PM PDT 24 |
Aug 06 07:27:20 PM PDT 24 |
121254575914 ps |
| T859 |
/workspace/coverage/default/14.sram_ctrl_bijection.2371169172 |
|
|
Aug 06 07:18:22 PM PDT 24 |
Aug 06 07:31:08 PM PDT 24 |
135434362950 ps |
| T860 |
/workspace/coverage/default/31.sram_ctrl_smoke.1319478756 |
|
|
Aug 06 07:21:24 PM PDT 24 |
Aug 06 07:22:47 PM PDT 24 |
14102356243 ps |
| T861 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2005200291 |
|
|
Aug 06 07:24:41 PM PDT 24 |
Aug 06 07:26:13 PM PDT 24 |
5860848875 ps |
| T862 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3108460659 |
|
|
Aug 06 07:19:47 PM PDT 24 |
Aug 06 07:22:01 PM PDT 24 |
4537880731 ps |
| T863 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3647077326 |
|
|
Aug 06 07:24:05 PM PDT 24 |
Aug 06 07:26:57 PM PDT 24 |
809826849 ps |
| T864 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2883221128 |
|
|
Aug 06 07:24:24 PM PDT 24 |
Aug 06 07:30:34 PM PDT 24 |
23599389395 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.984374803 |
|
|
Aug 06 07:25:12 PM PDT 24 |
Aug 06 07:25:22 PM PDT 24 |
367933505 ps |
| T866 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1803035885 |
|
|
Aug 06 07:23:20 PM PDT 24 |
Aug 06 07:24:06 PM PDT 24 |
50753129632 ps |
| T867 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2694800331 |
|
|
Aug 06 07:19:32 PM PDT 24 |
Aug 06 07:21:32 PM PDT 24 |
3075036647 ps |
| T103 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1586168324 |
|
|
Aug 06 07:22:48 PM PDT 24 |
Aug 06 07:25:25 PM PDT 24 |
9792405192 ps |
| T868 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.886009569 |
|
|
Aug 06 07:18:03 PM PDT 24 |
Aug 06 07:21:10 PM PDT 24 |
16320584037 ps |
| T869 |
/workspace/coverage/default/44.sram_ctrl_regwen.1822866135 |
|
|
Aug 06 07:24:23 PM PDT 24 |
Aug 06 07:29:51 PM PDT 24 |
8185480866 ps |
| T870 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.673535694 |
|
|
Aug 06 07:18:20 PM PDT 24 |
Aug 06 07:19:31 PM PDT 24 |
4720848615 ps |
| T871 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1340175859 |
|
|
Aug 06 07:25:36 PM PDT 24 |
Aug 06 07:27:04 PM PDT 24 |
6136294019 ps |
| T872 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1431373771 |
|
|
Aug 06 07:23:40 PM PDT 24 |
Aug 06 08:51:21 PM PDT 24 |
38648715202 ps |
| T873 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.573327 |
|
|
Aug 06 07:19:09 PM PDT 24 |
Aug 06 07:24:34 PM PDT 24 |
21566855840 ps |
| T874 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1410237716 |
|
|
Aug 06 07:23:04 PM PDT 24 |
Aug 06 07:23:08 PM PDT 24 |
1403908080 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_bijection.3055455073 |
|
|
Aug 06 07:20:53 PM PDT 24 |
Aug 06 07:53:14 PM PDT 24 |
280464246827 ps |
| T876 |
/workspace/coverage/default/35.sram_ctrl_bijection.3904738575 |
|
|
Aug 06 07:22:00 PM PDT 24 |
Aug 06 07:36:34 PM PDT 24 |
148321311895 ps |
| T877 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.778447468 |
|
|
Aug 06 07:18:41 PM PDT 24 |
Aug 06 07:32:15 PM PDT 24 |
28217664357 ps |
| T878 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.144994125 |
|
|
Aug 06 07:25:12 PM PDT 24 |
Aug 06 07:25:40 PM PDT 24 |
5121011013 ps |
| T879 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1085101445 |
|
|
Aug 06 07:24:39 PM PDT 24 |
Aug 06 07:24:43 PM PDT 24 |
741534994 ps |
| T880 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2424281826 |
|
|
Aug 06 07:19:32 PM PDT 24 |
Aug 06 07:20:04 PM PDT 24 |
22130002415 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3450249672 |
|
|
Aug 06 07:21:38 PM PDT 24 |
Aug 06 07:22:18 PM PDT 24 |
3054739985 ps |
| T882 |
/workspace/coverage/default/32.sram_ctrl_stress_all.365638511 |
|
|
Aug 06 07:21:42 PM PDT 24 |
Aug 06 08:51:02 PM PDT 24 |
186765051293 ps |
| T883 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4138265492 |
|
|
Aug 06 07:19:30 PM PDT 24 |
Aug 06 07:36:21 PM PDT 24 |
9094827155 ps |
| T884 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3981928720 |
|
|
Aug 06 07:21:36 PM PDT 24 |
Aug 06 07:34:45 PM PDT 24 |
31076681348 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_bijection.1057666637 |
|
|
Aug 06 07:18:41 PM PDT 24 |
Aug 06 07:35:09 PM PDT 24 |
41707717483 ps |
| T886 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4005314525 |
|
|
Aug 06 07:25:27 PM PDT 24 |
Aug 06 07:25:31 PM PDT 24 |
1612800400 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.338616117 |
|
|
Aug 06 07:19:04 PM PDT 24 |
Aug 06 07:19:14 PM PDT 24 |
1357494361 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_partial_access.801818290 |
|
|
Aug 06 07:18:48 PM PDT 24 |
Aug 06 07:19:31 PM PDT 24 |
783504299 ps |
| T889 |
/workspace/coverage/default/20.sram_ctrl_alert_test.138974170 |
|
|
Aug 06 07:19:29 PM PDT 24 |
Aug 06 07:19:30 PM PDT 24 |
43384618 ps |
| T29 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.1343444983 |
|
|
Aug 06 07:17:45 PM PDT 24 |
Aug 06 07:17:47 PM PDT 24 |
268969948 ps |
| T890 |
/workspace/coverage/default/13.sram_ctrl_alert_test.649939241 |
|
|
Aug 06 07:18:20 PM PDT 24 |
Aug 06 07:18:21 PM PDT 24 |
43613880 ps |
| T891 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.4067627082 |
|
|
Aug 06 07:20:12 PM PDT 24 |
Aug 06 07:20:15 PM PDT 24 |
679364140 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_smoke.1713957677 |
|
|
Aug 06 07:18:30 PM PDT 24 |
Aug 06 07:21:08 PM PDT 24 |
5297768109 ps |
| T893 |
/workspace/coverage/default/37.sram_ctrl_executable.3052936928 |
|
|
Aug 06 07:22:31 PM PDT 24 |
Aug 06 07:30:23 PM PDT 24 |
16854942294 ps |
| T894 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3040742580 |
|
|
Aug 06 07:17:51 PM PDT 24 |
Aug 06 07:20:48 PM PDT 24 |
5071586769 ps |
| T895 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3287233979 |
|
|
Aug 06 07:22:49 PM PDT 24 |
Aug 06 07:27:08 PM PDT 24 |
4152725147 ps |
| T896 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.4111162705 |
|
|
Aug 06 07:18:48 PM PDT 24 |
Aug 06 07:36:44 PM PDT 24 |
6734951541 ps |
| T897 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2689632296 |
|
|
Aug 06 07:20:53 PM PDT 24 |
Aug 06 07:49:02 PM PDT 24 |
47295178380 ps |
| T898 |
/workspace/coverage/default/27.sram_ctrl_executable.4016955449 |
|
|
Aug 06 07:20:31 PM PDT 24 |
Aug 06 07:40:13 PM PDT 24 |
34156121493 ps |
| T899 |
/workspace/coverage/default/21.sram_ctrl_bijection.2035814217 |
|
|
Aug 06 07:19:34 PM PDT 24 |
Aug 06 07:45:30 PM PDT 24 |
179590809457 ps |
| T900 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2122255866 |
|
|
Aug 06 07:18:09 PM PDT 24 |
Aug 06 07:19:39 PM PDT 24 |
12237061335 ps |
| T901 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1150143245 |
|
|
Aug 06 07:22:49 PM PDT 24 |
Aug 06 07:23:11 PM PDT 24 |
5280913389 ps |
| T902 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.173414791 |
|
|
Aug 06 07:20:31 PM PDT 24 |
Aug 06 07:25:45 PM PDT 24 |
21637935198 ps |
| T903 |
/workspace/coverage/default/26.sram_ctrl_alert_test.190797456 |
|
|
Aug 06 07:20:37 PM PDT 24 |
Aug 06 07:20:38 PM PDT 24 |
14037603 ps |
| T904 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2583489000 |
|
|
Aug 06 07:20:33 PM PDT 24 |
Aug 06 07:20:37 PM PDT 24 |
6712068275 ps |
| T905 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3250552331 |
|
|
Aug 06 07:21:38 PM PDT 24 |
Aug 06 07:36:04 PM PDT 24 |
71762362603 ps |
| T906 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1439159359 |
|
|
Aug 06 07:21:16 PM PDT 24 |
Aug 06 07:21:17 PM PDT 24 |
15171730 ps |
| T907 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.336866163 |
|
|
Aug 06 07:19:30 PM PDT 24 |
Aug 06 07:30:01 PM PDT 24 |
27405828351 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_bijection.2943563901 |
|
|
Aug 06 07:17:48 PM PDT 24 |
Aug 06 07:56:48 PM PDT 24 |
97376086787 ps |
| T909 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.461719097 |
|
|
Aug 06 07:23:06 PM PDT 24 |
Aug 06 07:23:53 PM PDT 24 |
737044350 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.743810853 |
|
|
Aug 06 07:20:31 PM PDT 24 |
Aug 06 07:24:43 PM PDT 24 |
20710356911 ps |
| T911 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3477473277 |
|
|
Aug 06 07:20:51 PM PDT 24 |
Aug 06 07:25:02 PM PDT 24 |
14726027376 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2243240238 |
|
|
Aug 06 07:18:20 PM PDT 24 |
Aug 06 07:25:25 PM PDT 24 |
6310486646 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1548498609 |
|
|
Aug 06 07:22:02 PM PDT 24 |
Aug 06 07:24:42 PM PDT 24 |
11324892682 ps |
| T914 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3890637751 |
|
|
Aug 06 07:20:50 PM PDT 24 |
Aug 06 07:20:57 PM PDT 24 |
1503474756 ps |
| T915 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.85258008 |
|
|
Aug 06 07:22:30 PM PDT 24 |
Aug 06 07:28:18 PM PDT 24 |
26696704742 ps |
| T916 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.4208434208 |
|
|
Aug 06 07:19:25 PM PDT 24 |
Aug 06 07:21:01 PM PDT 24 |
237933360601 ps |
| T917 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3451090101 |
|
|
Aug 06 07:18:19 PM PDT 24 |
Aug 06 07:18:27 PM PDT 24 |
1432579929 ps |
| T918 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2100750399 |
|
|
Aug 06 07:22:00 PM PDT 24 |
Aug 06 07:22:03 PM PDT 24 |
681537914 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1358558155 |
|
|
Aug 06 07:18:42 PM PDT 24 |
Aug 06 07:21:03 PM PDT 24 |
9733594102 ps |
| T920 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2796060357 |
|
|
Aug 06 07:21:18 PM PDT 24 |
Aug 06 07:24:33 PM PDT 24 |
7361872994 ps |
| T921 |
/workspace/coverage/default/0.sram_ctrl_alert_test.3077674497 |
|
|
Aug 06 07:17:45 PM PDT 24 |
Aug 06 07:17:46 PM PDT 24 |
36467158 ps |
| T922 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1504804345 |
|
|
Aug 06 07:22:15 PM PDT 24 |
Aug 06 07:23:21 PM PDT 24 |
2215123852 ps |
| T923 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1436823076 |
|
|
Aug 06 07:20:36 PM PDT 24 |
Aug 06 07:20:38 PM PDT 24 |
169288445 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2358894670 |
|
|
Aug 06 07:18:10 PM PDT 24 |
Aug 06 07:18:13 PM PDT 24 |
694223798 ps |
| T925 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1869568581 |
|
|
Aug 06 07:18:09 PM PDT 24 |
Aug 06 07:18:13 PM PDT 24 |
1355706806 ps |
| T926 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.822126403 |
|
|
Aug 06 07:18:27 PM PDT 24 |
Aug 06 07:18:31 PM PDT 24 |
360284752 ps |
| T927 |
/workspace/coverage/default/41.sram_ctrl_smoke.1139067340 |
|
|
Aug 06 07:23:20 PM PDT 24 |
Aug 06 07:23:31 PM PDT 24 |
3017550783 ps |
| T928 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3643985772 |
|
|
Aug 06 07:18:22 PM PDT 24 |
Aug 06 07:20:29 PM PDT 24 |
3802680131 ps |
| T929 |
/workspace/coverage/default/10.sram_ctrl_smoke.169910772 |
|
|
Aug 06 07:18:21 PM PDT 24 |
Aug 06 07:18:55 PM PDT 24 |
687943049 ps |
| T930 |
/workspace/coverage/default/45.sram_ctrl_regwen.1241650537 |
|
|
Aug 06 07:24:41 PM PDT 24 |
Aug 06 07:34:41 PM PDT 24 |
5540972562 ps |
| T931 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.605727245 |
|
|
Aug 06 07:22:30 PM PDT 24 |
Aug 06 07:23:34 PM PDT 24 |
115754968867 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1709884477 |
|
|
Aug 06 07:25:28 PM PDT 24 |
Aug 06 07:25:33 PM PDT 24 |
5603019123 ps |
| T933 |
/workspace/coverage/default/9.sram_ctrl_smoke.2630731939 |
|
|
Aug 06 07:18:22 PM PDT 24 |
Aug 06 07:18:36 PM PDT 24 |
2236366486 ps |
| T934 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3246427054 |
|
|
Aug 06 07:25:27 PM PDT 24 |
Aug 06 07:25:35 PM PDT 24 |
761730976 ps |
| T935 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.4214650435 |
|
|
Aug 06 07:20:54 PM PDT 24 |
Aug 06 07:24:20 PM PDT 24 |
94103840474 ps |
| T936 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1866174680 |
|
|
Aug 06 07:18:43 PM PDT 24 |
Aug 06 07:18:47 PM PDT 24 |
3071809283 ps |
| T937 |
/workspace/coverage/default/12.sram_ctrl_bijection.2005891752 |
|
|
Aug 06 07:18:20 PM PDT 24 |
Aug 06 07:54:37 PM PDT 24 |
149059256116 ps |
| T938 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1798089546 |
|
|
Aug 06 07:21:18 PM PDT 24 |
Aug 06 07:21:24 PM PDT 24 |
831350705 ps |
| T939 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4074441355 |
|
|
Aug 06 07:24:42 PM PDT 24 |
Aug 06 07:31:31 PM PDT 24 |
30193967208 ps |
| T940 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4292356703 |
|
|
Aug 06 07:18:06 PM PDT 24 |
Aug 06 07:19:52 PM PDT 24 |
3447329093 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2903744047 |
|
|
Aug 06 05:23:52 PM PDT 24 |
Aug 06 05:23:53 PM PDT 24 |
13575811 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2693563773 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:29 PM PDT 24 |
162112941 ps |
| T69 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.798091958 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:27 PM PDT 24 |
15294116079 ps |
| T64 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1885872657 |
|
|
Aug 06 05:24:04 PM PDT 24 |
Aug 06 05:24:07 PM PDT 24 |
259626942 ps |
| T113 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2136075587 |
|
|
Aug 06 05:23:36 PM PDT 24 |
Aug 06 05:24:29 PM PDT 24 |
25179226285 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3864678133 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:43 PM PDT 24 |
1296964281 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.693144234 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:27 PM PDT 24 |
24750156 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1387050909 |
|
|
Aug 06 05:23:55 PM PDT 24 |
Aug 06 05:23:59 PM PDT 24 |
378394862 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1836355721 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:23:37 PM PDT 24 |
25903888 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3974520578 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
31565534 ps |
| T943 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.774629684 |
|
|
Aug 06 05:23:52 PM PDT 24 |
Aug 06 05:23:56 PM PDT 24 |
39824750 ps |
| T78 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2403749683 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:00 PM PDT 24 |
22636061 ps |
| T79 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1907096098 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:24:31 PM PDT 24 |
29290535681 ps |
| T115 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3601538862 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:23:38 PM PDT 24 |
54854517 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1422353027 |
|
|
Aug 06 05:23:25 PM PDT 24 |
Aug 06 05:23:26 PM PDT 24 |
262635323 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4074188328 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:52 PM PDT 24 |
47915498 ps |
| T65 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3623218096 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
327080759 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.129407328 |
|
|
Aug 06 05:23:39 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
14253367 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1300452951 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:31 PM PDT 24 |
106128994 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3727366191 |
|
|
Aug 06 05:23:24 PM PDT 24 |
Aug 06 05:23:25 PM PDT 24 |
26678235 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.868446756 |
|
|
Aug 06 05:23:31 PM PDT 24 |
Aug 06 05:23:35 PM PDT 24 |
347734129 ps |
| T949 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1581919188 |
|
|
Aug 06 05:23:56 PM PDT 24 |
Aug 06 05:23:59 PM PDT 24 |
1217662628 ps |
| T81 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2620351734 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:24:07 PM PDT 24 |
14764252124 ps |
| T82 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3739461399 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:00 PM PDT 24 |
47121178 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3010722991 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:03 PM PDT 24 |
703392695 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3166909378 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
60571868 ps |
| T951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1071252266 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:39 PM PDT 24 |
40410383 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1968762717 |
|
|
Aug 06 05:23:34 PM PDT 24 |
Aug 06 05:23:38 PM PDT 24 |
616059643 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1598562770 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
1396898520 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3419096270 |
|
|
Aug 06 05:24:04 PM PDT 24 |
Aug 06 05:25:00 PM PDT 24 |
7350793322 ps |
| T954 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2008483617 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:23:58 PM PDT 24 |
372706143 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.238220328 |
|
|
Aug 06 05:23:34 PM PDT 24 |
Aug 06 05:24:03 PM PDT 24 |
7536486978 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2462603472 |
|
|
Aug 06 05:24:04 PM PDT 24 |
Aug 06 05:25:09 PM PDT 24 |
44183271780 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4022245651 |
|
|
Aug 06 05:23:24 PM PDT 24 |
Aug 06 05:23:25 PM PDT 24 |
59439784 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.898717367 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:00 PM PDT 24 |
25748697 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3706373442 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:42 PM PDT 24 |
722599950 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1616535726 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
15772226 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.397711102 |
|
|
Aug 06 05:23:35 PM PDT 24 |
Aug 06 05:23:37 PM PDT 24 |
99034188 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2399620056 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:23:59 PM PDT 24 |
20130626 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2114362104 |
|
|
Aug 06 05:23:36 PM PDT 24 |
Aug 06 05:23:36 PM PDT 24 |
34171200 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3312862643 |
|
|
Aug 06 05:23:23 PM PDT 24 |
Aug 06 05:23:24 PM PDT 24 |
18547286 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3825451942 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:26 PM PDT 24 |
39473905 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1758185048 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:24:05 PM PDT 24 |
3892626044 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1607555900 |
|
|
Aug 06 05:23:57 PM PDT 24 |
Aug 06 05:23:58 PM PDT 24 |
13457934 ps |
| T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1653256091 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:00 PM PDT 24 |
24683789 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.741007601 |
|
|
Aug 06 05:23:31 PM PDT 24 |
Aug 06 05:23:32 PM PDT 24 |
48163073 ps |
| T126 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4145310463 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
166101613 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4146406946 |
|
|
Aug 06 05:23:36 PM PDT 24 |
Aug 06 05:24:04 PM PDT 24 |
52879524920 ps |
| T969 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1502924432 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
26042000 ps |
| T970 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.641724426 |
|
|
Aug 06 05:23:56 PM PDT 24 |
Aug 06 05:23:57 PM PDT 24 |
23704257 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.836333764 |
|
|
Aug 06 05:23:29 PM PDT 24 |
Aug 06 05:23:30 PM PDT 24 |
47205855 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1921634781 |
|
|
Aug 06 05:23:28 PM PDT 24 |
Aug 06 05:24:20 PM PDT 24 |
14969010753 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2817051764 |
|
|
Aug 06 05:24:00 PM PDT 24 |
Aug 06 05:24:01 PM PDT 24 |
29815033 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1937816087 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:27 PM PDT 24 |
73267335 ps |
| T90 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3030257901 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:24:27 PM PDT 24 |
15408934819 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2703217250 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
1148944367 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.201757983 |
|
|
Aug 06 05:23:31 PM PDT 24 |
Aug 06 05:23:32 PM PDT 24 |
15564575 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3508860888 |
|
|
Aug 06 05:23:58 PM PDT 24 |
Aug 06 05:24:00 PM PDT 24 |
391506780 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3237474596 |
|
|
Aug 06 05:23:53 PM PDT 24 |
Aug 06 05:23:54 PM PDT 24 |
13996978 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.426682674 |
|
|
Aug 06 05:23:57 PM PDT 24 |
Aug 06 05:24:01 PM PDT 24 |
65414567 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3095018963 |
|
|
Aug 06 05:23:58 PM PDT 24 |
Aug 06 05:24:01 PM PDT 24 |
3082628573 ps |
| T136 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1821601255 |
|
|
Aug 06 05:23:57 PM PDT 24 |
Aug 06 05:23:58 PM PDT 24 |
144038803 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1126814084 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
138084078 ps |
| T91 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2739632271 |
|
|
Aug 06 05:23:39 PM PDT 24 |
Aug 06 05:23:39 PM PDT 24 |
122483471 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.216852474 |
|
|
Aug 06 05:23:56 PM PDT 24 |
Aug 06 05:23:56 PM PDT 24 |
45822778 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3165993155 |
|
|
Aug 06 05:24:00 PM PDT 24 |
Aug 06 05:24:01 PM PDT 24 |
19963335 ps |
| T132 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.964394043 |
|
|
Aug 06 05:23:59 PM PDT 24 |
Aug 06 05:24:01 PM PDT 24 |
413047550 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4277757458 |
|
|
Aug 06 05:23:25 PM PDT 24 |
Aug 06 05:23:29 PM PDT 24 |
2230439530 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1107633336 |
|
|
Aug 06 05:24:04 PM PDT 24 |
Aug 06 05:24:07 PM PDT 24 |
62770841 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.454541812 |
|
|
Aug 06 05:23:34 PM PDT 24 |
Aug 06 05:23:36 PM PDT 24 |
266337706 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.677045692 |
|
|
Aug 06 05:23:36 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
1380555626 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1247904334 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:27 PM PDT 24 |
13434885 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4137403123 |
|
|
Aug 06 05:23:36 PM PDT 24 |
Aug 06 05:23:37 PM PDT 24 |
41323215 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.363712065 |
|
|
Aug 06 05:23:56 PM PDT 24 |
Aug 06 05:23:58 PM PDT 24 |
158213191 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1847931958 |
|
|
Aug 06 05:23:24 PM PDT 24 |
Aug 06 05:23:30 PM PDT 24 |
1495178367 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2475612042 |
|
|
Aug 06 05:23:35 PM PDT 24 |
Aug 06 05:23:36 PM PDT 24 |
16549832 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3424088877 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
356088535 ps |
| T130 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.987026677 |
|
|
Aug 06 05:23:50 PM PDT 24 |
Aug 06 05:23:52 PM PDT 24 |
176141195 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.938701107 |
|
|
Aug 06 05:23:24 PM PDT 24 |
Aug 06 05:23:26 PM PDT 24 |
309645312 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1661070054 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:39 PM PDT 24 |
21948696 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2829967712 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:52 PM PDT 24 |
32838169 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3782712966 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:27 PM PDT 24 |
193198733 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1110008103 |
|
|
Aug 06 05:23:52 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
117656768 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4139894678 |
|
|
Aug 06 05:23:26 PM PDT 24 |
Aug 06 05:23:53 PM PDT 24 |
16756228385 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2728826432 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:23:55 PM PDT 24 |
24117665 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3614046033 |
|
|
Aug 06 05:23:54 PM PDT 24 |
Aug 06 05:23:56 PM PDT 24 |
93963791 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1036333891 |
|
|
Aug 06 05:24:04 PM PDT 24 |
Aug 06 05:24:07 PM PDT 24 |
387710287 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1189632845 |
|
|
Aug 06 05:23:27 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
47310290 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2295907323 |
|
|
Aug 06 05:23:39 PM PDT 24 |
Aug 06 05:24:07 PM PDT 24 |
14773434259 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.473494170 |
|
|
Aug 06 05:23:25 PM PDT 24 |
Aug 06 05:23:28 PM PDT 24 |
27145522 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.910611403 |
|
|
Aug 06 05:23:35 PM PDT 24 |
Aug 06 05:23:39 PM PDT 24 |
367811835 ps |
| T127 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3313696636 |
|
|
Aug 06 05:23:34 PM PDT 24 |
Aug 06 05:23:37 PM PDT 24 |
459033793 ps |
| T1001 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2992486819 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:54 PM PDT 24 |
440126180 ps |
| T1002 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4004909619 |
|
|
Aug 06 05:23:39 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
68187727 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.481533838 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:23:41 PM PDT 24 |
355455363 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.17092716 |
|
|
Aug 06 05:23:30 PM PDT 24 |
Aug 06 05:23:32 PM PDT 24 |
130126580 ps |
| T1005 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2925901915 |
|
|
Aug 06 05:23:38 PM PDT 24 |
Aug 06 05:23:40 PM PDT 24 |
35944303 ps |
| T1006 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2450256666 |
|
|
Aug 06 05:23:34 PM PDT 24 |
Aug 06 05:23:35 PM PDT 24 |
36832790 ps |
| T1007 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3279368326 |
|
|
Aug 06 05:23:51 PM PDT 24 |
Aug 06 05:23:52 PM PDT 24 |
19909750 ps |
| T1008 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1838494096 |
|
|
Aug 06 05:23:37 PM PDT 24 |
Aug 06 05:23:38 PM PDT 24 |
95866059 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3635051249 |
|
|
Aug 06 05:23:24 PM PDT 24 |
Aug 06 05:23:25 PM PDT 24 |
20009741 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1105332820 |
|
|
Aug 06 05:23:23 PM PDT 24 |
Aug 06 05:23:50 PM PDT 24 |
15421349985 ps |